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31. 发明授权

US06609232B2 Logic compound method and logic compound apparatus 失效
标题翻译：逻辑复合法和逻辑复合器
公开(公告)号：US06609232B2
公开(公告)日：2003-08-19
申请号：US09791818
申请日：2001-02-26
申请人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
发明人： Teppei Hirotsu , Ryo Fujita , Kotaro Shimamura , Hiromichi Yamada , Dai Fujii , Haruyuki Nakayama
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.
摘要翻译：在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

32. 发明授权

US5623435A Arithmetic unit capable of performing concurrent operations for high speed operation 失效
标题翻译：算术单元能够执行高速运行的并发操作
公开(公告)号：US5623435A
公开(公告)日：1997-04-22
申请号：US371998
申请日：1995-01-12
申请人： Hidehito Takewa , Hiromichi Yamada , Takashi Hotta , Kotaro Shimamura
发明人： Hidehito Takewa , Hiromichi Yamada , Takashi Hotta , Kotaro Shimamura
IPC分类号： G06F7/50 , G06F7/52 , G06F7/535 , G06F7/537 , G06F7/57
CPC分类号： G06F7/535 , G06F7/483 , G06F7/485 , G06F7/5375 , G06F7/4873 , G06F7/49936 , G06F7/49957
摘要： An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values; has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.
摘要翻译：一个算术单元，接受两个数值，并通过使用两个数值执行一个操作; 具有用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法的加法器 - 减法器; 用于执行归一化处理的归一化器，其中相加或相减结果的尾数部分被移位，使得在结果中重新显现的高阶数字可以到达预定位置，并且其中结果的指数部分根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置，其中，在相加或相减结果的尾数部分超过预定数量的数字的条件下，尾数部分的位数根据预先指定的舍入模式而减少。舍入装置与加法器 - 减法器或归一化器的执行并行，通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。

33. 发明授权

US06986029B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06986029B2
公开(公告)日：2006-01-10
申请号：US10201249
申请日：2002-07-24
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F7/06 , G06F15/76
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

34. 发明申请

US20050198471A1 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 审中-公开
标题翻译：用于读出压缩指令代码的微控制器和用于压缩指令代码并存储在其中的程序存储器
公开(公告)号：US20050198471A1
公开(公告)日：2005-09-08
申请号：US11117509
申请日：2005-04-29
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
摘要翻译：微控制器包括用于存储出现在程序中的指令代码的字典存储器和用于存储从程序中包括的每个指令代码转换的压缩代码的压缩代码存储器。每个压缩代码的字长足够长以识别程序中包含的所有指令代码。每个压缩代码具有指示存储相关联的指令代码的字典存储器中的地址的值。微控制器响应于指定代码读取请求，其指定压缩代码的地址以读取存储在压缩代码存储器中的指定地址中的压缩代码，并且随后读取存储在由压缩代码存储器指示的地址中的指令代码字典内存中的压缩代码。

35. 发明授权

US5408426A Arithmetic unit capable of performing concurrent operations for high speed operation 失效
标题翻译：算术单元能够执行高速运行的并发操作
公开(公告)号：US5408426A
公开(公告)日：1995-04-18
申请号：US037654
申请日：1993-03-17
申请人： Hidehito Takewa , Hiromichi Yamada , Takashi Hotta , Kotaro Shimamura
发明人： Hidehito Takewa , Hiromichi Yamada , Takashi Hotta , Kotaro Shimamura
IPC分类号： G06F7/50 , G06F7/52 , G06F7/535 , G06F7/537 , G06F7/57 , G06F7/38
CPC分类号： G06F7/535 , G06F7/483 , G06F7/485 , G06F7/5375 , G06F7/4873 , G06F7/49936 , G06F7/49957
摘要： An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.
摘要翻译：接受两个数值并通过使用两个数值执行操作的算术单元具有加法器 - 减法器，用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法运算; 用于执行归一化处理的归一化器，其中相加或相减结果的尾数部分被移位，使得在结果中重新显现的高阶数字可以到达预定位置，并且其中结果的指数部分根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置，其中，在相加或相减结果的尾数部分超过预定数量的数字的条件下，尾数部分的位数根据预先指定的舍入模式而减少。舍入装置与加法器 - 减法器或归一化器的执行并行，通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。

36. 发明申请

US20050080492A1 Fail-safe controller 失效
标题翻译：故障安全控制器
公开(公告)号：US20050080492A1
公开(公告)日：2005-04-14
申请号：US10891360
申请日：2004-07-13
申请人： Kotaro Shimamura , Naohiro Ikeda , Takeshi Takehara
发明人： Kotaro Shimamura , Naohiro Ikeda , Takeshi Takehara
IPC分类号： G06F11/18 , G05B9/03 , G05B13/02
CPC分类号： G05B9/03
摘要： A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operations; a plurality of data storage elements for storing respective results of the arithmetic and logical operations of the plurality of the processors; a comparator for comparing the results of the arithmetic and logical operations of the plurality of the processors stored in the plurality of the data storage elements; and a comparison record storage element for storing a record of the comparison results of the comparator.
摘要翻译：接收设备状态的输入的控制器，执行预定的算术和逻辑运算，并输出设备的控制信号，并配备有用于执行算术和逻辑运算的多个处理器; 多个数据存储元件，用于存储多个处理器的算术和逻辑运算的各个结果; 比较器，用于比较存储在多个数据存储元件中的多个处理器的算术和逻辑运算的结果; 以及用于存储比较器的比较结果的记录的比较记录存储元件。

37. 发明授权

US06850854B2 Semiconductor production system 失效
标题翻译：半导体生产系统
公开(公告)号：US06850854B2
公开(公告)日：2005-02-01
申请号：US10444981
申请日：2003-05-27
申请人： Hidemitsu Naya , Rikio Tomiyoshi , Shigeo Moriyama , Mutsumi Kikuchi , Kotaro Shimamura
发明人： Hidemitsu Naya , Rikio Tomiyoshi , Shigeo Moriyama , Mutsumi Kikuchi , Kotaro Shimamura
IPC分类号： G01R31/26 , G01R31/28 , G03F7/20 , H01L21/00 , H01L21/02 , H01L21/027 , H01L21/66 , G06F19/00
CPC分类号： H01L21/67225 , G03F7/70508 , G03F7/70991 , G05B19/418 , G05B19/41855 , G05B2219/31323 , G05B2219/31326 , G05B2219/45031 , H01L21/67276 , H04L67/1097 , Y02P90/185 , Y02P90/24 , Y02P90/265
摘要： A semiconductor production system has a semiconductor manufacturing apparatus having an exposure unit, a control unit for controlling the exposure unit and a storage device; a semiconductor inspection apparatus having an observation unit, a control unit for controlling the observation unit and a storage device; and a storage device commonly used by the semiconductor manufacturing apparatus and the semiconductor inspection apparatus. The manufacturing apparatus, the inspection apparatus and the commonly used storage device are interconnected via a storage area network. With the semiconductor manufacturing apparatus and the storage device linked together via the storage area network, a large volume of image data or design data can be communicated at high speed, thus improving the system throughput.
摘要翻译：半导体制造系统具有具有曝光单元的半导体制造装置，用于控制曝光单元的控制单元和存储装置; 具有观察单元的半导体检查装置，用于控制观察单元的控制单元和存储装置; 以及半导体制造装置和半导体检查装置通常使用的存储装置。制造装置，检查装置和常用的存储装置经由存储区域网互连。随着半导体制造装置和存储装置经由存储区域网络连接在一起，可以高速地传送大量图像数据或设计数据，从而提高系统吞吐量。

38. 发明授权

US6038683A Replicated controller and fault recovery method thereof 失效
标题翻译：复制控制器及其故障恢复方法
公开(公告)号：US6038683A
公开(公告)日：2000-03-14
申请号：US40146
申请日：1998-03-17
申请人： Kotaro Shimamura , Yuuichiro Morita , Yoshitaka Takahashi , Takashi Hotta , Hiroyasu Satou , Shigeta Ueda , Akira Bando , Hirokazu Suzuki , Koji Sakamoto
发明人： Kotaro Shimamura , Yuuichiro Morita , Yoshitaka Takahashi , Takashi Hotta , Hiroyasu Satou , Shigeta Ueda , Akira Bando , Hirokazu Suzuki , Koji Sakamoto
IPC分类号： G05B9/03 , G06F11/18 , H02M7/48 , G06F11/00
CPC分类号： G06F11/182 , G05B9/03 , G06F11/184 , G06F11/188 , Y10S707/99953
摘要： A replicated controller and a fault recovery method therefor which can restore a faulty system to a normal state without interrupting operation of an equipment, even in an equipment controller performing processing with short operating periods.In a fault recovery method for a replicated controller, control data is divided into a plurality of blocks on the basis of dependency of the blocks, and a plurality of blocks are transferred in a sequential order of superiority of the dependency from the normally operating system to the faulty system in a period over a plurality of operating periods. BY this, even in an equipment controller performing processing at a short operating period, the system, in which failure is caused, can be restored into normal state without interrupting operation of the equipment.
摘要翻译：复制控制器及其故障恢复方法，即使在执行短操作周期的处理的设备控制器中，也可以将故障系统恢复到正常状态而不中断设备的操作。在复制控制器的故障恢复方法中，基于块的依赖性将控制数据划分为多个块，并且以从依赖关系的正常操作系统的优越性的顺序传送多个块在多个操作期间内的故障系统。由此，即使是在短时间内进行处理的设备控制器中，也可以在不中断设备的运转的情况下将导致故障的系统恢复到正常状态。

39. 发明申请

US20090024777A1 ARBITER AND ARBITRATION METHOD OF MULTIPLE DATA ACCESSES 失效
标题翻译：多数据访问的ARBITER和仲裁方法
公开(公告)号：US20090024777A1
公开(公告)日：2009-01-22
申请号：US12134038
申请日：2008-06-05
申请人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
发明人： Teppei Hirotsu , Kotaro Shimamura , Teruaki Sakata , Noboru Sugihara
IPC分类号： G06F13/366
CPC分类号： G06F13/366
摘要： There is provided a technique which reduces an average processing time of low-priority accesses with suppressing an average delay increase of a high-priority access processing even in a case where high-priority access request and a low-request access request are simultaneously generated to a shared access processing unit and high-priority accesses are continuously generated. And, there is provided an access arbitration equipment comprising: an issued access request retention unit; a first interval determination circuit; and a second interval determination circuit. In a case where the first interval determination circuit determines that an interval is generated between an issued access processing and a most prior access processing and a second interval determination circuit determines that no interval is generated between the issued access processing and a second-prior access request, the priority order of the most prior access request and the second-prior access request is changed.
摘要翻译：提供了一种技术，即使在高优先级访问请求和低请求访问请求被同时生成的情况下，也可以抑制高优先级访问处理的平均延迟增加来降低低优先级访问的平均处理时间，共享访问处理单元和高优先级访问被连续生成。并且，提供了一种访问仲裁设备，包括：发布的访问请求保留单元; 第一间隔确定电路; 和第二间隔确定电路。在第一间隔确定电路确定在发出的访问处理和最先进的访问处理之间产生间隔的情况下，并且第二间隔确定电路确定在所发行的访问处理和第二先前的访问请求之间不产生间隔，最先进的访问请求和第二个访问请求的优先顺序被改变。

40. 发明申请

US20080177855A1 Packet communication apparatus 审中-公开
标题翻译：分组通信装置
公开(公告)号：US20080177855A1
公开(公告)日：2008-07-24
申请号：US12076686
申请日：2008-03-21
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Kotaro Shimamura , Yasuwo Watanabe
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L69/161 , H04L69/162 , H04L69/22
摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.
摘要翻译：包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少加载CPU并增加通信处理速度。

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