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31. 发明授权

US07212475B2 Method and apparatus for tilt correction and tilt driving signal generating circuit 失效
标题翻译：用于倾斜校正和倾斜驱动信号发生电路的方法和装置
公开(公告)号：US07212475B2
公开(公告)日：2007-05-01
申请号：US10774395
申请日：2004-02-10
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G11B7/00
CPC分类号： G11B7/0956
摘要： In the tilt correction method, information about inclination of an object lens relative to an information recording medium is acquired. A direct current signal Sdc for correcting the inclination is produced based on the information. An alternating current signal Sac having a prescribed signal characteristic is superposed onto the direct current signal Sdc to produce a driving signal Sout. The driving signal Sout is supplied to a driving mechanism to correct the inclination of the object lens against friction.
摘要翻译：在倾斜校正方法中，获取关于物镜相对于信息记录介质的倾斜度的信息。基于该信息产生用于校正倾斜度的直流电流信号Sdc。具有规定信号特性的交流信号Sac叠加在直流信号Sdc上，以产生驱动信号Sout。驱动信号Sout被提供给驱动机构以校正物镜倾斜摩擦。

32. 发明授权

US07091943B2 Liquid crystal display device having a video correction signal generator 有权
标题翻译：具有视频校正信号发生器的液晶显示装置
公开(公告)号：US07091943B2
公开(公告)日：2006-08-15
申请号：US10717270
申请日：2003-11-19
申请人： Hiroshi Takeda , Shinji Kiyomatsu
发明人： Hiroshi Takeda , Shinji Kiyomatsu
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G2300/08 , G09G2310/0275 , G09G2320/0219 , G09G2320/0223 , G09G2320/0252
摘要： A liquid crystal display device includes a plurality of pixels arranged in a matrix, a drain line provided for each column of the plurality of pixels, a gate line provided for each row of the plurality of pixels, and an output buffer to output a video signal supplied to the drain line. Also provided is a video correction signal generator to superpose a correction signal on the output signal of the output buffer.
摘要翻译：一种液晶显示装置，包括以矩阵形式排列的多个像素，为多个像素中的每列设置的漏极线，为多个像素中的每一行提供的栅极线以及输出视频信号的输出缓冲器供给到排水管路。还提供了一种视频校正信号发生器，用于将校正信号叠加在输出缓冲器的输出信号上。

33. 发明授权

US07090502B2 Board connecting component and three-dimensional connecting structure using thereof 失效
标题翻译：板连接部件及其三维连接结构
公开(公告)号：US07090502B2
公开(公告)日：2006-08-15
申请号：US11118403
申请日：2005-05-02
申请人： Masahiro Ono , Shigeru Kondou , Kazuhiro Nishikawa , Kazuto Nishida , Hiroyuki Inoue , Osamu Miyazaki , Hiroshi Takeda , Tsuneyuki Ejima
发明人： Masahiro Ono , Shigeru Kondou , Kazuhiro Nishikawa , Kazuto Nishida , Hiroyuki Inoue , Osamu Miyazaki , Hiroshi Takeda , Tsuneyuki Ejima
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： H05K1/144 , H01L2224/16225 , H01L2924/19105 , H01R12/52 , H05K3/3426 , H05K2201/042 , H05K2201/10189 , H05K2201/10424 , H05K2201/2018
摘要： The present invention includes a plurality of lead terminals made of a conductive material having spring elasticity; and insulative housing that buries a part of the region of lead terminal and fixedly retains a plurality of lead terminals in an arrangement having been set in advance. Lead terminal is composed of a buried part that is a part of lead terminal buried in housing; bottom end joint that is extended from one end of the buried part, is exposed through bottom end surface of housing, and extracted in width direction of bottom end surface; and flexibly changing part that is exposed from another end of the buried part through one wall surface orthogonal to bottom end surface, and is extended along this wall surface to top end surface facing to bottom end surface, being spaced from wall surface and top end surface.
摘要翻译：本发明包括由具有弹性弹性的导电材料制成的多个引线端子; 绝缘壳体，其埋设引线端子区域的一部分，并且在预先设置的布置中固定地保持多个引线端子。引线端子由掩埋在壳体中的引线端子的一部分构成; 从埋藏部分的一端延伸的底端接头通过壳体的底端表面暴露，并在底端表面的宽度方向上提取; 以及通过与底端表面正交的一个壁面暴露于埋藏部分的另一端的柔性变化部分，并且沿着该壁表面延伸到面向底端表面的顶端表面，与壁表面和顶端表面间隔开。

34. 发明授权

US06809712B2 Drive circuit of liquid crystal display, having clip circuit before polarity inversion circuit 有权
标题翻译：液晶显示驱动电路，具有极性反转电路前的钳位电路
公开(公告)号：US06809712B2
公开(公告)日：2004-10-26
申请号：US09802215
申请日：2001-03-08
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G09G500
CPC分类号： G09G3/3614 , G09G3/3648 , G09G2320/0257 , G09G2320/0276
摘要： A drive circuit of an LCD is disclosed, by which no image signal having a voltage level over the dynamic range of the video amplifier, and thus erroneous operation of the video amplifier is prevented, thereby supplying normal image signals to the LCD. The drive circuit comprises a clip circuit for clipping the amplitude range of the voltage of a picture signal input from an input terminal; a polarity inversion circuit for receiving the picture signal whose amplitude range was clipped by the clip circuit, and for converting the picture signal so that an inverted signal and a non-inverted signal are alternately assigned to each dot; and a video amplifier for amplifying the voltage level of the converted picture signal by a predetermined amplification degree.
摘要翻译：公开了一种LCD的驱动电路，通过该驱动电路不会影响具有超过视频放大器的动态范围的电压电平，从而防止视频放大器的错误操作，从而向LCD提供正常图像信号。驱动电路包括用于限制从输入端子输入的图像信号的电压的幅度范围的限幅电路; 极性反转电路，用于接收由幅度电路限幅的幅度范围的图像信号，并将图像信号转换为每个点交替分配反相信号和非反相信号; 以及用于将经转换的图像信号的电压电平放大预定放大度的视频放大器。

35. 发明授权

US06292867B1 Data processing system 有权
标题翻译：数据处理系统
公开(公告)号：US06292867B1
公开(公告)日：2001-09-18
申请号：US09641913
申请日：2000-08-21
申请人： Osamu Nishii , Nobuyuki Hayashi , Noriharu Hiratsuka , Tetsuhiko Okada , Hiroshi Takeda
发明人： Osamu Nishii , Nobuyuki Hayashi , Noriharu Hiratsuka , Tetsuhiko Okada , Hiroshi Takeda
IPC分类号： G06F1202
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译：一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

36. 发明授权

US5873122A Memory system performing fast access to a memory location by omitting transfer of a redundant address 失效
标题翻译：存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问
公开(公告)号：US5873122A
公开(公告)日：1999-02-16
申请号：US815600
申请日：1997-03-12
申请人： Osamu Nishii , Nobuyuki Hayashi , Noriharu Hiratsuka , Tetsuhiko Okada , Hiroshi Takeda
发明人： Osamu Nishii , Nobuyuki Hayashi , Noriharu Hiratsuka , Tetsuhiko Okada , Hiroshi Takeda
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译：一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

37. 发明授权

US5696540A Display controller 失效
标题翻译：显示控制器
公开(公告)号：US5696540A
公开(公告)日：1997-12-09
申请号：US799889
申请日：1991-12-02
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/14 , G09G5/32 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , G09G5/397 , G09G1/00
CPC分类号： G09G5/36 , G09G5/363 , G09G5/39 , G09G5/397
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译：在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性通过将单位时钟分割成预定数量以高速功能和多功能显示。当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示。所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

38. 发明授权

US5673398A Data transfer control method, and peripheral circuit, data processor and data processing system for the method 失效
标题翻译：数据传输控制方法，外围电路，数据处理器和数据处理系统的方法
公开(公告)号：US5673398A
公开(公告)日：1997-09-30
申请号：US369722
申请日：1995-01-06
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F13/42 , G06F12/00 , G06F13/00 , G06F13/16 , G11C7/22 , G06F13/36
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
摘要翻译：存储器1响应于CPU 2的接收请求（200,201和202）与其中并入的自激振荡器102的振荡输出同步并且根据所述访问请求执行其内部操作，并且输出响应请求 103，用于与其内部操作同步地对所述CPU的所述访问请求。 CPU执行对存储器的访问请求，并且从外部获取数据或者响应于来自所访问的存储器的响应请求103并根据所述访问请求的种类而将数据输出到外部。

39. 发明授权

US5557760A Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus 失效
标题翻译：集成电路数据处理器，包括用于在不停用地址总线的情况下去激活数据总线的驱动的控制引脚
公开(公告)号：US5557760A
公开(公告)日：1996-09-17
申请号：US117681
申请日：1993-09-08
申请人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
发明人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
IPC分类号： G06F12/08 , G06F13/40 , G06F13/20
CPC分类号： G06F12/0893 , G06F13/4072
摘要： A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.
摘要翻译：用于具有高速缓存RAM和主存储器的数据处理系统中的处理器具有控制引脚，用于在写周期期间停用数据总线的驱动而不停用地址总线的驱动。在无需附加地址存储电路的执行写入操作之后的高速缓存存储操作期间，该能力是有用的。特别地，在高速缓存存储操作期间，处理器可以驱动地址总线，同时处理器的数据总线的控制是浮动的。然后，主存储器中的数据可以放在数据总线上并传输到高速缓存中。一旦将数据传输到高速缓冲存储器，可以完成原始写入操作。

40. 发明授权

US5333666A Method for manufacturing a resin pattern, and a method for vacuum sealed molding process using resin pattern same 失效
标题翻译：树脂图案的制造方法以及使用树脂图案的真空密封成型方法
公开(公告)号：US5333666A
公开(公告)日：1994-08-02
申请号：US968410
申请日：1992-10-29
申请人： Hideo Ootomo , Hiroshi Takeda , Shunichiro Yachi
发明人： Hideo Ootomo , Hiroshi Takeda , Shunichiro Yachi
IPC分类号： B22C7/00 , B22C7/02 , B22C7/05 , B22C9/03 , H02K5/06
CPC分类号： B22C7/02
摘要： A method for manufacturing a resin pattern, which does not break films in a vacuum sealed molding process and does not have secular deterioration even after repeated usages wherein a covering film is tightly contacted to an original pattern by vacuum suction, an amount of particle bodies are packed onto the covering film in a flask under the above described condition, upper portion of the flask is covered by another covering film, the tight contact of the covering film to the original pattern is released by returning the reduced pressure to normal pressure, internal pressure of the packed particle bodies is reduced, a mold cavity is formed by removing the original pattern from the packed particle bodies, a predetermined number of double solid bodies are set up in the mold cavity in the packed particle bodies which is previously turned reversely so as to be the cavity at upper side, molding resin is poured into the mold cavity, cores in the double solid bodies are withdrawn for forming through holes after hardening the resin, and the resin pattern is obtained by returning the internal reduced pressure of the packed particle bodies to normal pressure for breaking down the packed particle bodies.
摘要翻译：一种树脂图案的制造方法，其在真空密封成型工艺中不会破裂膜，即使在重复使用之后也不具有长期劣化，其中通过真空吸附将覆盖膜紧密接触原始图案，颗粒体的量为在上述条件下在烧瓶中包装到覆盖膜上，烧瓶的上部被另一个覆盖膜覆盖，通过将减压恢复到正常压力，内部压力来释放覆盖膜与原始图案的紧密接触的填充颗粒体减少，通过从填充颗粒体中除去原始图案形成模腔，将预定数量的双固体物体设置在预先反向旋转的填充颗粒体中的模腔中，以便作为上侧的空腔，将模塑树脂倒入模腔中，双固体中的芯被取出成型在树脂硬化后通孔，树脂图案是通过将填充颗粒体的内部减压返回正常压力来分解填充颗粒体而得到的。

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