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31. 发明申请

US20130092893A1 NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储元件及其制造方法
公开(公告)号：US20130092893A1
公开(公告)日：2013-04-18
申请号：US13704663
申请日：2011-06-30
申请人： Yoshio Kawashima , Takumi Mikawa
发明人： Yoshio Kawashima , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/1666 , H01L27/2436 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： The method includes: forming a lower electrode layer above a substrate; forming a variable resistance layer on the lower electrode layer; forming an upper electrode layer on the variable resistance layer; forming a hard mask layer on the upper electrode layer; forming a photoresist mask on the hard mask layer; forming a hard mask by performing etching on the hard mask layer using the photoresist mask; and forming a nonvolatile memory element by performing etching on the upper electrode layer, the variable resistance layer, and the lower electrode layer, using the hard mask. In the forming of a photoresist mask, the photoresist mask is formed to have corner portions which recede toward the center portion in planar view.
摘要翻译：该方法包括：在基板上形成下电极层; 在下电极层上形成可变电阻层; 在所述可变电阻层上形成上电极层; 在上电极层上形成硬掩模层; 在硬掩模层上形成光刻胶掩模; 通过使用光致抗蚀剂掩模在硬掩模层上进行蚀刻来形成硬掩模; 以及通过使用硬掩模对上电极层，可变电阻层和下电极层进行蚀刻来形成非易失性存储元件。在光致抗蚀剂掩模的形成中，光致抗蚀剂掩模形成为具有在平面视图中朝向中心部分后退的角部。

32. 发明申请

US20120063201A1 NONVOLATILE MEMORY ELEMENT, PRODUCTION METHOD THEREFOR, DESIGN SUPPORT METHOD THEREFOR, AND NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储元件，其生产方法，其设计支持方法和非易失性存储器件
公开(公告)号：US20120063201A1
公开(公告)日：2012-03-15
申请号：US13320654
申请日：2011-03-16
申请人： Yukio Hayakawa , Takumi Mikawa , Yoshio Kawashima , Takeki Ninomiya
发明人： Yukio Hayakawa , Takumi Mikawa , Yoshio Kawashima , Takeki Ninomiya
IPC分类号： G11C11/00 , H01L21/8239 , G06F17/50 , H01L45/00
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes at least two layers: a first variable resistance layer (1161) including a first transition metal oxide (116b); and a second variable resistance layer (1162) including a second transition metal oxide (116a) and a third transition metal oxide (116c). The second transition metal oxide (116a) has an oxygen deficiency higher than either oxygen deficiency of the first transition metal oxide (116b) or the third transition metal oxide (116c), and the second transition metal oxide (116a) and the third transition metal oxide (116c) are in contact with the first variable resistance layer (1161).
摘要翻译：可以以低电压初始化的非易失性存储元件包括位于下电极（105）和上电极（107）之间的可变电阻层（116），并且具有基于施加在这些电极之间的电信号而可逆地改变的电阻值。可变电阻层（116）包括至少两层：包括第一过渡金属氧化物（116b）的第一可变电阻层（1161）; 和包括第二过渡金属氧化物（116a）和第三过渡金属氧化物（116c）的第二可变电阻层（1162）。第二过渡金属氧化物（116a）的缺氧高于第一过渡金属氧化物（116b）或第三过渡金属氧化物（116c）的氧缺乏，第二过渡金属氧化物（116a）和第三过渡金属氧化物（116c）与第一可变电阻层（1161）相接触。

33. 发明申请

US20110220863A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110220863A1
公开(公告)日：2011-09-15
申请号：US13129215
申请日：2010-09-13
申请人： Takumi Mikawa , Yoshio Kawashima
发明人： Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/04 , H01L27/101 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage.The nonvolatile memory device (10) in the present invention includes: a lower electrode (105) formed above a substrate (100); a first variable resistance layer (106a) formed above the lower electrode (105) and comprising a transitional metal oxide; a second variable resistance layer (106b) formed above the first variable resistance layer (106a) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer (106a); and an upper electrode (107) formed above the second variable resistance layer (106b), wherein a step (106ax) is formed in an interface between the first variable is resistance layer (106a) and the second variable resistance layer (106b). The second variable resistance layer (106b) is formed covering the step (106ax) and has a bend (106bx) above the step (106ax).
摘要翻译：通过降低断开电压以实现电阻变化并抑制断开电压的变化来实现存储器的小型化和增加的容量。本发明的非易失性存储器件（10）包括：形成在衬底（100）上方的下电极（105）; 形成在所述下电极（105）上方并且包含过渡金属氧化物的第一可变电阻层（106a）形成在第一可变电阻层（106a）上方的第二可变电阻层（106b），并且包括具有比第一可变电阻层（106a）的过渡金属氧化物高的氧含量的过渡金属氧化物; 以及形成在所述第二可变电阻层（106b）上方的上电极（107），其中在所述第一可变电阻层（106a）和所述第二可变电阻层（106b）之间的界面中形成台阶（106ax）。第二可变电阻层（106b）被形成为覆盖台阶（106ax）并且在台阶（106ax）上方具有弯曲部（106bx）。

34. 发明授权

US07981760B2 Method for manufacturing nonvolatile storage element and method for manufacturing nonvolatile storage device 有权
标题翻译：非易失性存储元件的制造方法及其制造方法
公开(公告)号：US07981760B2
公开(公告)日：2011-07-19
申请号：US12669812
申请日：2009-05-07
申请人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
发明人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.
摘要翻译：一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

35. 发明授权

US07960770B2 Nonvolatile memory element array with storing layer formed by resistance variable layers 有权
标题翻译：具有由电阻变化层形成的存储层的非易失存储元件阵列
公开(公告)号：US07960770B2
公开(公告)日：2011-06-14
申请号：US12445380
申请日：2007-10-12
申请人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
发明人： Takumi Mikawa , Takeshi Takagi , Yoshio Kawashima , Koji Arita
IPC分类号： H01L29/76
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1683
摘要： A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).
摘要翻译：下电极（22）设置在半导体芯片基板（26）上。下部电极（22）从上方被第一层间绝缘层（27）覆盖。第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

36. 发明申请

US20100190313A1 METHOD FOR MANUFACTURING NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE 有权
标题翻译：制造非易失性存储元件的方法和制造非易失存储器件的方法
公开(公告)号：US20100190313A1
公开(公告)日：2010-07-29
申请号：US12669812
申请日：2009-05-07
申请人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
发明人： Yoshio Kawashima , Takumi Mikawa , Takeshi Takagi , Koji Arita
IPC分类号： H01L21/8246
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.
摘要翻译：一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 形成掩模层，形成预定的形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

37. 发明授权

US08785238B2 Nonvolatile memory element and method for manufacturing same 有权
标题翻译：非易失存储元件及其制造方法
公开(公告)号：US08785238B2
公开(公告)日：2014-07-22
申请号：US13704663
申请日：2011-06-30
申请人： Yoshio Kawashima , Takumi Mikawa
发明人： Yoshio Kawashima , Takumi Mikawa
IPC分类号： H01L29/02
CPC分类号： H01L45/1666 , H01L27/2436 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： The method includes: forming a lower electrode layer above a substrate; forming a variable resistance layer on the lower electrode layer; forming an upper electrode layer on the variable resistance layer; forming a hard mask layer on the upper electrode layer; forming a photoresist mask on the hard mask layer; forming a hard mask by performing etching on the hard mask layer using the photoresist mask; and forming a nonvolatile memory element by performing etching on the upper electrode layer, the variable resistance layer, and the lower electrode layer, using the hard mask. In the forming of a photoresist mask, the photoresist mask is formed to have corner portions which recede toward the center portion in planar view.
摘要翻译：该方法包括：在基板上形成下电极层; 在下电极层上形成可变电阻层; 在所述可变电阻层上形成上电极层; 在上电极层上形成硬掩模层; 在硬掩模层上形成光刻胶掩模; 通过使用光致抗蚀剂掩模在硬掩模层上进行蚀刻来形成硬掩模; 以及通过使用硬掩模对上电极层，可变电阻层和下电极层进行蚀刻来形成非易失性存储元件。在光致抗蚀剂掩模的形成中，光致抗蚀剂掩模形成为具有在平面视图中朝向中心部分后退的角部。

38. 发明授权

US08530321B2 Variable resistance element and manufacturing method thereof 有权
标题翻译：可变电阻元件及其制造方法
公开(公告)号：US08530321B2
公开(公告)日：2013-09-10
申请号：US13515761
申请日：2010-12-14
申请人： Takeki Ninomiya , Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
发明人： Takeki Ninomiya , Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L21/20
CPC分类号： C23C26/00 , C23C28/00 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.
摘要翻译：可变电阻元件包括当M是过渡金属元素时，O是氧，x和y是满足y> x的正数; 下电极当相对于M的含量比为O时，形成在下电极上并包含MOx的第一氧化物层; 当相对于M的含量比为O时，形成在第一氧化物层上并包含MOy的第二氧化物层; 形成在所述第二氧化物层上的上电极; 形成在上电极上并具有不同于上电极的组成的组成的导电材料的保护层; 形成为覆盖保护层的层间绝缘层; 以及形成在贯穿层间绝缘层的上接触孔内部的上接触插塞。

39. 发明申请

US20130119344A1 NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失存储元件及其制造方法
公开(公告)号：US20130119344A1
公开(公告)日：2013-05-16
申请号：US13810800
申请日：2011-10-06
申请人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
发明人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/101 , H01L45/08 , H01L45/146 , H01L45/1608 , H01L45/1625
摘要： A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
摘要翻译：可变电阻非易失性存储元件包括：第一电极; 第二电极; 以及可变电阻层，其具有基于施加在所述电极之间的电信号而可逆地变化的电阻值，其中所述可变电阻层具有通过堆叠第一过渡金属氧化物层，第二过渡金属氧化物层和第三过渡金属氧化物层而形成的结构过渡金属氧化物层，第一过渡金属氧化物层具有以MOx表示的组成（其中M是过渡金属，O是氧），第二过渡金属氧化物层具有以MOy表示的组成（其中x> y ）和具有表示为MOz（其中y> z）的组成的第三过渡金属氧化物层。

40. 发明授权

US08242479B2 Nonvolatile memory apparatus and manufacturing method thereof 有权
标题翻译：非易失性存储装置及其制造方法
公开(公告)号：US08242479B2
公开(公告)日：2012-08-14
申请号：US12742841
申请日：2008-11-14
申请人： Yoshio Kawashima , Takumi Mikawa , Ryoko Miyanaga , Takeshi Takagi
发明人： Yoshio Kawashima , Takumi Mikawa , Ryoko Miyanaga , Takeshi Takagi
IPC分类号： H01L29/02
CPC分类号： H01L27/101 , G11C13/0002 , G11C2213/72 , H01L27/24
摘要： A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.
摘要翻译：非易失性存储器件包括分别形成在第一布线（11）与第二布线（14）交叉的横截面处的通孔（12），以及各自包括电流控制层（13b）的电流控制元件（13），第一电极层（13a）和第二电极层（13c），使得电流控制层（13b）夹在第一电极层（13a）和第二电极层（13c）之间，其中电阻可变元件（15）设置在其内通孔（12）分别设置成覆盖通孔（12），电流控制层（13b）被设置成覆盖第一电极层（13a），第二电极层（13c）设置在电流控制层（13b）上，第二导线的导线层（14a）设置在第二电极层（13c）上，第二导线（14）各自包括电流控制层（13b），第二电极层（13c）和第二wi的导线层（14a）回覆。

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