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31. 发明申请

US20120205737A1 SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION 有权
标题翻译： SHIELDED GATE TRENCH MOSFET器件和制造
公开(公告)号：US20120205737A1
公开(公告)日：2012-08-16
申请号：US13456406
申请日：2012-04-26
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

32. 发明申请

US20120187472A1 TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT 有权
标题翻译： TRENCH MOS和SGT的TRENCH POLY ESD形成
公开(公告)号：US20120187472A1
公开(公告)日：2012-07-26
申请号：US13010427
申请日：2011-01-20
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P—N—P or N—P—N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.
摘要翻译：描述半导体器件及其制造方法。形成在半导体衬底中的沟槽部分地填充所述沟槽，其中半导体材料对沟槽的底部和侧面进行排列，在沟槽的中间留下间隙，沿沟槽沿纵向延伸。位于间隙下方的半导体材料的第一部分掺杂有第一导电类型的掺杂剂。间隙填充有电介质材料。位于电介质材料两侧的沟槽侧面的半导体材料的第二部分掺杂有第二导电类型的掺杂剂。掺杂形成沿着沟槽纵向延伸的P-N-P或N-P-N结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。

33. 发明授权

US08193580B2 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US08193580B2
公开(公告)日：2012-06-05
申请号：US12583191
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

34. 发明申请

US20110220990A1 SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT 有权
标题翻译： SHIELDED GATE TRENCH MOS与改进的来源PICKUP布局
公开(公告)号：US20110220990A1
公开(公告)日：2011-09-15
申请号：US12722384
申请日：2010-03-11
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

35. 发明申请

US20110039383A1 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US20110039383A1
公开(公告)日：2011-02-17
申请号：US12583192
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.
摘要翻译：一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模，金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

36. 发明授权

US09887283B2 Process method and structure for high voltage MOSFETs 有权
公开(公告)号：US09887283B2
公开(公告)日：2018-02-06
申请号：US13892191
申请日：2013-05-10
申请人： Yongping Ding , Lei Zhang , Hong Chang , Jongoh Kim , John Chen
发明人： Yongping Ding , Lei Zhang , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/78 , H01L21/2652 , H01L21/26586 , H01L29/66348 , H01L29/66666 , H01L29/7827
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

37. 发明授权

US08580676B2 Multiple layer barrier metal for device component formed in contact trench 有权
标题翻译：用于器件部件的多层阻挡金属形成在接触沟槽中
公开(公告)号：US08580676B2
公开(公告)日：2013-11-12
申请号：US13361486
申请日：2012-01-30
申请人： Hong Chang , John Chen , Limin Weng , Wenjun Li
发明人： Hong Chang , John Chen , Limin Weng , Wenjun Li
IPC分类号： H01L21/4763
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.
摘要翻译：形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。阻挡金属可以包括第一和第二金属层。第一金属层可以靠近接触沟槽的侧壁和底部。第一金属层可以包括氮化物。第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

38. 发明授权

US08502302B2 Integrating Schottky diode into power MOSFET 有权
标题翻译：将肖特基二极管集成到功率MOSFET中
公开(公告)号：US08502302B2
公开(公告)日：2013-08-06
申请号：US13098852
申请日：2011-05-02
申请人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
摘要翻译：半导体器件包括多个沟槽，包括有源区域中的有源栅极沟槽和栅极流道/终止沟槽以及在有源区域外部的终止区域中的屏蔽电极拾取沟槽。栅极流道/终止沟槽包括限定位于有源区域之外的台面的一个或多个沟槽。在多个沟槽中形成第一导电区域。在限定台面的沟槽中形成中间介质区域和端接保护区域。在限定台面的沟槽部分中形成第二导电区域。第二导电区域通过中间介电区域与第一导电区域电隔离。对第二导电区域进行第一电接触，并且在屏蔽电极拾取沟槽中对第一导电区域进行第二电接触。在台面内形成一个或多个肖特基二极管。

39. 发明授权

US08476676B2 Trench poly ESD formation for trench MOS and SGT 有权
标题翻译：沟槽MOS和SGT的沟槽聚合物ESD形成
公开(公告)号：US08476676B2
公开(公告)日：2013-07-02
申请号：US13010427
申请日：2011-01-20
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P-N-P or N-P-N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.
摘要翻译：描述半导体器件及其制造方法。形成在半导体衬底中的沟槽部分地填充所述沟槽，其中半导体材料对沟槽的底部和侧面进行排列，在沟槽的中间留下间隙，沿沟槽沿纵向延伸。位于间隙下方的半导体材料的第一部分掺杂有第一导电类型的掺杂剂。间隙填充有电介质材料。位于电介质材料两侧的沟槽侧面的半导体材料的第二部分掺杂有第二导电类型的掺杂剂。掺杂形成沿着沟槽纵向延伸的P-N-P或N-P-N结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。

40. 发明授权

US08299494B2 Nanotube semiconductor devices 有权
标题翻译：纳米管半导体器件
公开(公告)号：US08299494B2
公开(公告)日：2012-10-30
申请号：US12484170
申请日：2009-06-12
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L29/74 , H01L31/111 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/0886 , H01L21/26586 , H01L27/0623 , H01L27/0629 , H01L27/0664 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0676 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/36 , H01L29/365 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/41775 , H01L29/4236 , H01L29/42368 , H01L29/66136 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/8613 , H01L29/872 , H01L29/8725
摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.
摘要翻译：半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层其中第二外延层电连接到第二半导体层。第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度选择平均掺杂浓度以在操作中实现电荷平衡。

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