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31. 发明申请

US20130216003A1 RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：用于时钟和数据恢复（CDR）电路的可复位电压控制振荡器（VCO）及相关系统和方法
公开(公告)号：US20130216003A1
公开(公告)日：2013-08-22
申请号：US13465057
申请日：2012-05-07
申请人： Jingcheng Zhuang , Nam V. Dang
发明人： Jingcheng Zhuang , Nam V. Dang
IPC分类号： H04L25/02
CPC分类号： H04L25/02 , H03K3/0322 , H03L7/0995 , H03L2207/06 , H04L7/033
摘要： Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data stream. However, a clock signal of the data stream needs to be recovered to sample the data stream since the data stream may not be accompanied by the clock signal. To recover the clock signal from the data stream, the CDR circuit may have a resettable VCO configured to generate a clock output. The sampler and the resettable VCO may be operably associated so that the sampler samples the data stream in the data path based on the clock output. The resettable VCO can be reset to adjust a clock phase of the clock output and help reduce sampling errors resulting from drift of the clock output and/or the data stream.
摘要翻译：公开了时钟和数据恢复（CDR）电路和可复位的压控振荡器（VCO）。在一个实施例中，CDR电路包括被配置为在数据路径中接收数据流并对数据流进行采样的采样器。然而，需要恢复数据流的时钟信号以采样数据流，因为数据流可能不伴随时钟信号。为了从数据流恢复时钟信号，CDR电路可以具有被配置为产生时钟输出的可复位VCO。采样器和可重置VCO可以可操作地相关联，使得采样器基于时钟输出对数据路径中的数据流进行采样。可复位的VCO可以被复位以调整时钟输出的时钟相位，并有助于减少由于时钟输出和/或数据流的漂移而导致的采样错误。

32. 发明申请

US20130187708A1 Wide Input Bit-Rate, Power Efficient PWM Decoder 失效
标题翻译：宽输入比特率，功率有效的PWM解码器
公开(公告)号：US20130187708A1
公开(公告)日：2013-07-25
申请号：US13469261
申请日：2012-05-11
申请人： Nam V. Dang , Terrence B. Remple , Zhiqin Chen
发明人： Nam V. Dang , Terrence B. Remple , Zhiqin Chen
IPC分类号： H03K9/08
CPC分类号： H03K9/08 , H04L25/4902
摘要： A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.
摘要翻译：接收脉宽调制（PWM）信号，并且在PWM信号的时间间隔中，当PWM信号处于第一电平时，第一计数增加，并且当PWM信号为第二时，第二计数增加水平。在时间间隔结束时，将第一计数与第二计数进行比较，并且基于比较，生成解码位。可选地，增加第一计数是通过启用增加第一计数器的第一振荡器，并且通过启用增加第二计数器的第二振荡器来递增第二计数。

33. 发明申请

US20120068774A1 Amplitude Control for Oscillator 失效
标题翻译：振荡器振幅控制
公开(公告)号：US20120068774A1
公开(公告)日：2012-03-22
申请号：US12886719
申请日：2010-09-21
申请人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
发明人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/36 , H03L3/00
摘要： An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.
摘要翻译：振幅控制电路包括一对峰值检测器。一对峰值检测器响应于电压参考发生器。幅度控制电路被配置为响应于晶体振荡器的振荡信号，并被配置为产生控制信号以控制振荡信号的振幅。

34. 发明授权

US08564365B2 Wide input bit-rate, power efficient PWM decoder 失效
标题翻译：宽输入比特率，功率有效的PWM解码器
公开(公告)号：US08564365B2
公开(公告)日：2013-10-22
申请号：US13469261
申请日：2012-05-11
申请人： Nam V. Dang , Terrence B. Remple , Zhiqin Chen
发明人： Nam V. Dang , Terrence B. Remple , Zhiqin Chen
IPC分类号： H03K9/08
CPC分类号： H03K9/08 , H04L25/4902
摘要： A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.
摘要翻译：接收脉宽调制（PWM）信号，并且在PWM信号的时间间隔中，当PWM信号处于第一电平时，第一计数增加，并且当PWM信号为第二时，第二计数增加水平。在时间间隔结束时，将第一计数与第二计数进行比较，并且基于比较，生成解码位。可选地，增加第一计数是通过启用增加第一计数器的第一振荡器，并且通过启用增加第二计数器的第二振荡器来递增第二计数。

35. 发明授权

US5949472A Method and apparatus for tuning channels for CATV and television applications 失效
标题翻译：用于调谐CATV和电视应用的频道的方法和装置
公开(公告)号：US5949472A
公开(公告)日：1999-09-07
申请号：US762726
申请日：1996-12-10
申请人： Nam V. Dang , Lewis E. Adams, III
发明人： Nam V. Dang , Lewis E. Adams, III
IPC分类号： H03D7/16 , H04N5/44 , H04N7/10 , H04N7/16
CPC分类号： H04N5/4446 , H03D7/163 , H04N7/102 , H04N7/16
摘要： A method of tuning channels for television and community antenna television (CATV) devices includes the step of receiving a radio frequency input (RFI) signal having at least one carrier signal at frequency f.sub.s associated with a selected broadcast channel. The RFI signal is up-converted by m to a first intermediate frequency wherein the carrier signal is located at f.sub.s +m. The first intermediate frequency is filtered. The filtered first intermediate frequency is down-converted by n to a second intermediate frequency wherein the second intermediate frequency includes the carrier signal at f.sub.s +m-n. Additional methods for improving the reception of the selected channel include the step of varying m and n in order to avoid frequency-dependent anomalies within the pass band of the filter. For digital communications, m and n are varied in accordance with an error rate of the digital communications in order to reduce the error rate of the digital communications.
摘要翻译：一种用于电视和社区天线电视（CATV）设备的调谐频道的方法包括接收具有与所选择的广播频道相关联的频率fs处的至少一个载波信号的射频输入（RFI）信号的步骤。 RFI信号由m上变频到第一中频，其中载波信号位于fs + m。第一个中频被过滤。滤波后的第一中频由n下变频到第二中频，其中第二中频包括fs + m-n处的载波信号。用于改善所选频道的接收的附加方法包括改变m和n的步骤，以避免滤波器的通带内的频率相关异常。对于数字通信，m和n根据数字通信的错误率而变化，以便减少数字通信的错误率。

36. 发明授权

US08289090B2 Amplitude control for oscillator 失效
标题翻译：振荡器幅度控制
公开(公告)号：US08289090B2
公开(公告)日：2012-10-16
申请号：US12886719
申请日：2010-09-21
申请人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
发明人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
IPC分类号： H03B5/36 , H03G1/00 , H03L5/00
CPC分类号： H03L5/00 , H03B5/36 , H03L3/00
摘要： An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.
摘要翻译：振幅控制电路包括一对峰值检测器。一对峰值检测器响应于电压参考发生器。幅度控制电路被配置为响应于晶体振荡器的振荡信号，并被配置为产生控制信号以控制振荡信号的振幅。

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