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31. 外观设计

USD973138S1 Toy piano 有权
公开(公告)号：USD973138S1
公开(公告)日：2022-12-20
申请号：US29759949
申请日：2020-11-26
申请人： Xi Li
设计人： Xi Li

32. 发明授权

US08492280B1 Method for simultaneously forming features of different depths in a semiconductor substrate 失效
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08492280B1
公开(公告)日：2013-07-23
申请号：US13465050
申请日：2012-05-07
申请人： Habib Hichri , Xi Li , Richard S. Wise
发明人： Habib Hichri , Xi Li , Richard S. Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

33. 发明授权

US08165928B2 Managing events within supply chain networks 有权
标题翻译：管理供应链网络中的事件
公开(公告)号：US08165928B2
公开(公告)日：2012-04-24
申请号：US09919567
申请日：2001-07-30
申请人： John J. Dooley , Xi Li
发明人： John J. Dooley , Xi Li
IPC分类号： G06Q10/00
CPC分类号： G06Q10/08 , G06K2017/0045 , G06Q10/06 , G06Q10/0637 , G06Q10/087 , G06Q20/203 , G06Q20/208
摘要： A supply chain network system comprises a site data appliance (SDA) and a Universal Data Appliance Protocol (UDAP) adapter coupled with one or more data source equipments (DSE). The SDA collects specification information comprising event information from the one or more DSE. A server is coupled with the SDA in the supply chain network. In response to the server requesting the specification information, the SDA sends to the server the specification information in a Description Document. A data center (DC) is coupled with the server in the supply chain network. The DC receives the Description Document and maps the event information in the specification information with event handlers. A mapping of the event information with the event handlers is sent from the DC to the server. When an event is generated by the one or more DSE, the map is used to select an appropriate event handler to execute.
摘要翻译：供应链网络系统包括与一个或多个数据源设备（DSE）耦合的站点数据设备（SDA）和通用数据设备协议（UDAP）适配器。 SDA从一个或多个DSE收集包括事件信息的规范信息。服务器与供应链网络中的SDA配合使用。响应于请求规范信息的服务器，SDA向服务器发送描述文档中的规范信息。数据中心（DC）与供应链网络中的服务器相连。 DC接收描述文档，并使用事件处理程序将规范信息中的事件信息映射。将事件信息与事件处理程序的映射从DC发送到服务器。当一个或多个DSE生成事件时，该映射用于选择要执行的适当的事件处理程序。

34. 发明授权

US08008160B2 Method and structure for forming trench DRAM with asymmetric strap 有权
标题翻译：用不对称带形成沟槽DRAM的方法和结构
公开(公告)号：US08008160B2
公开(公告)日：2011-08-30
申请号：US12017154
申请日：2008-01-21
申请人： Kangguo Cheng , Xi Li , Richard Wise
发明人： Kangguo Cheng , Xi Li , Richard Wise
IPC分类号： H01L21/20
CPC分类号： H01L21/26586 , H01L27/10867 , H01L29/7833
摘要： A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.
摘要翻译：提供了一种形成具有单面埋入带的沟槽器件结构的方法。该方法包括在半导体衬底中形成深沟槽，所述深沟槽具有第一侧部分和第二侧部分; 在所述深沟槽上沉积节点电介质，其中所述节点电介质覆盖所述第一侧部分和所述第二侧部分; 在所述节点电介质上沉积第一导电层; 以一定角度进行离子注入或离子轰击到所述节点电介质的一部分中，从而从所述深沟槽的所述第一侧部分移除所述节点电介质的所述部分; 以及在所述第一导电层上沉积第二导电层，其中所述第二导电层超出所述半导体衬底的一部分。还提供了具有单面埋置带的沟槽器件结构。该器件结构包括其中具有深沟槽的半导体衬底; 以及顺序地设置在所述深沟槽上的第一导电层和第二导电层，其中所述第二导电层向外延伸到所述半导体衬底的一部分中。

35. 发明授权

US07892928B2 Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers 有权
标题翻译：形成不对称间隔物的方法和使用不对称间隔物制造半导体器件的方法
公开(公告)号：US07892928B2
公开(公告)日：2011-02-22
申请号：US11690258
申请日：2007-03-23
申请人： Kangguo Cheng , Xi Li , Richard Stephen Wise
发明人： Kangguo Cheng , Xi Li , Richard Stephen Wise
IPC分类号： H01L21/336
CPC分类号： H01L21/67069 , H01J37/32733 , H01J2237/20207 , H01L21/3086 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/7848 , H01L29/78654
摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
摘要翻译：制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述保形层暴露于所述反应性离子的通量，直到所述保形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上离开第一间隔物，并在所述第二侧壁上留下第二间隔物，所述第一间隔物比第二间隔物薄。

36. 发明授权

US07683416B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07683416B2
公开(公告)日：2010-03-23
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

37. 发明授权

US07682922B2 Post STI trench capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US07682922B2
公开(公告)日：2010-03-23
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

38. 发明申请

US20090017584A1 PROCESS FOR FINFET SPACER FORMATION 有权
标题翻译： FINFET间隙形成工艺
公开(公告)号：US20090017584A1
公开(公告)日：2009-01-15
申请号：US11776710
申请日：2007-07-12
申请人： Kangguo Cheng , Xi Li , Richard S. Wise
发明人： Kangguo Cheng , Xi Li , Richard S. Wise
IPC分类号： H01L29/786
CPC分类号： H01L29/66795 , H01L29/785
摘要： A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.
摘要翻译：用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。

39. 发明申请

US20080233691A1 METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS 有权
标题翻译：形成不对称间隔的方法和使用不对称间隔制作半导体器件的方法
公开(公告)号：US20080233691A1
公开(公告)日：2008-09-25
申请号：US11690258
申请日：2007-03-23
申请人： Kangguo Cheng , Xi Li , Richard Stephen Wise
发明人： Kangguo Cheng , Xi Li , Richard Stephen Wise
IPC分类号： H01L21/8234
CPC分类号： H01L21/67069 , H01J37/32733 , H01J2237/20207 , H01L21/3086 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/7848 , H01L29/78654
摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
摘要翻译：制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述保形层暴露于所述反应性离子的通量，直到所述保形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上离开第一间隔物，并在所述第二侧壁上留下第二间隔物，所述第一间隔物比第二间隔物更薄。

40. 发明申请

US20080173918A1 Post STI Trench Capacitor 失效
标题翻译：后STI沟槽电容器
公开(公告)号：US20080173918A1
公开(公告)日：2008-07-24
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

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