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31. 发明申请

US20160079115A1 Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns 有权
标题翻译：使用衬垫层制造半导体器件以避免损害底层图案的方法
公开(公告)号：US20160079115A1
公开(公告)日：2016-03-17
申请号：US14703556
申请日：2015-05-04
申请人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
发明人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76843 , H01L2221/1063
摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
摘要翻译：一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案，衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

32. 发明授权

US08669185B2 Method of tailoring conformality of Si-containing film 有权
标题翻译：定制含Si膜的一致性的方法
公开(公告)号：US08669185B2
公开(公告)日：2014-03-11
申请号：US12847848
申请日：2010-07-30
申请人： Shigeyuki Onizawa , Woo-Jin Lee , Hideaki Fukuda , Kunitoshi Namba
发明人： Shigeyuki Onizawa , Woo-Jin Lee , Hideaki Fukuda , Kunitoshi Namba
IPC分类号： H01L21/311 , H01L21/302 , H01L21/31 , C23C16/00
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/45523 , H01L21/02167 , H01L21/02274 , H01L21/0228
摘要： A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.
摘要翻译：定制沉积在图案化表面上的膜的共形性的方法包括：（I）通过PEALD或脉冲PECVD在图案化表面上沉积膜; （II）蚀刻所述膜，其中所述蚀刻以脉冲或脉冲进行，其中所述图案的所述膜上的所述膜的蚀刻速率与所述图案的侧壁上的膜的蚀刻速率的比率被控制为蚀刻脉冲持续时间和蚀刻脉冲数以增加膜的共形度; 和（III）重复（I）和（II）以满足目标膜厚度。

33. 发明申请

US20130315585A1 PASSIVE WAVELENGTH DIVISION MULTIPLEXING DEVICE FOR AUTOMATIC WAVELENGTH LOCKING AND SYSTEM THEREOF 有权
标题翻译：用于自动波长锁定的被动波段多路复用器件及其系统
公开(公告)号：US20130315585A1
公开(公告)日：2013-11-28
申请号：US13988837
申请日：2010-11-30
申请人： Ki-Woon Na , Woo-Jin Lee , Kwon-Hoon Han , Seung-Rog Choi , Tae-Hyeong Kim , Young-Ouk Noh
发明人： Ki-Woon Na , Woo-Jin Lee , Kwon-Hoon Han , Seung-Rog Choi , Tae-Hyeong Kim , Young-Ouk Noh
IPC分类号： H04J14/02
CPC分类号： H04J14/02 , H04B10/50575 , H04B10/506 , H04B10/572 , H04J14/0228 , H04J14/0272 , H04J14/0282
摘要： The present invention relates to a passive wavelength division multiplexing device for automatic wavelength locking and a system thereof including an optical multiplexer, an optical filter, an integrated optical receiver monitor, and a tunable optical transmitter.Through wavelength locking that adjusts a wavelength of an optical signal, which changes according to an external environment such as a temperature change, into a wavelength of an optical signal having the maximum optical intensity, communication quality may be maximized by securing a stable communication channel, a locking time and a communication channel setting time may be reduced, and more robust locking may be guaranteed.
摘要翻译：本发明涉及一种用于自动波长锁定的被动波分复用装置及其系统，包括光复用器，滤光器，集成光接收器监视器和可调光发射器。通过波长锁定，其将根据诸如温度变化的外部环境变化的光信号的波长调整为具有最大光强度的光信号的波长，通过确保稳定的通信信道可以使通信质量最大化，可以减少锁定时间和通信信道设置时间，并且可以保证更加鲁棒的锁定。

34. 发明申请

US20120028469A1 METHOD OF TAILORING CONFORMALITY OF Si-CONTAINING FILM 有权
标题翻译：定制含Si膜的一致性的方法
公开(公告)号：US20120028469A1
公开(公告)日：2012-02-02
申请号：US12847848
申请日：2010-07-30
申请人： Shigeyuki Onizawa , Woo-Jin Lee , Hideaki Fukuda , Kunitoshi Namba
发明人： Shigeyuki Onizawa , Woo-Jin Lee , Hideaki Fukuda , Kunitoshi Namba
IPC分类号： H01L21/311
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/45523 , H01L21/02167 , H01L21/02274 , H01L21/0228
摘要： A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.
摘要翻译：定制沉积在图案化表面上的膜的共形性的方法包括：（I）通过PEALD或脉冲PECVD在图案化表面上沉积膜; （II）蚀刻所述膜，其中所述蚀刻以脉冲或脉冲进行，其中所述图案的所述膜上的所述膜的蚀刻速率与所述图案的侧壁上的膜的蚀刻速率的比率被控制为蚀刻脉冲持续时间和蚀刻脉冲数以增加膜的共形度; 和（III）重复（I）和（II）以满足目标膜厚度。

35. 发明申请

US20100167203A1 Resist underlayer composition and method of manufacturing semiconductor integrated circuit device using the same 有权
标题翻译：抗蚀剂底层组合物和使用其制造半导体集成电路器件的方法
公开(公告)号：US20100167203A1
公开(公告)日：2010-07-01
申请号：US12654737
申请日：2009-12-30
申请人： Hyeon-Mo Cho , Sang-Kyun Kim , Chang-Soo Woo , Mi-Young Kim , Sang-Ran Koh , Hui-Chan Yun , Woo-Jin Lee , Jong-Seob Kim
发明人： Hyeon-Mo Cho , Sang-Kyun Kim , Chang-Soo Woo , Mi-Young Kim , Sang-Ran Koh , Hui-Chan Yun , Woo-Jin Lee , Jong-Seob Kim
IPC分类号： G03F7/20 , G03F7/004
CPC分类号： G03F7/0752 , C08G77/12 , C08G77/14 , C08G77/16 , C08G77/18 , C08G77/20 , C08G77/24 , C08G77/26 , C08G77/50 , C08G77/52 , C08G77/70 , C08K5/0008 , C08L83/04 , C08L83/14 , C09D183/04 , C09D183/14 , G03F7/0757 , G03F7/09 , G03F7/091 , G03F7/094 , G03F7/11 , G03F7/30 , G03F7/36
摘要： A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the composition including a solvent and an organosilane polymer, the organosilane polymer being a condensation polymerization product of at least one first compound represented by Chemical Formulae 1 and 2 and at least one second compound represented by Chemical Formulae 3 to 5.
摘要翻译：抗蚀剂下层组合物和半导体集成电路器件的制造方法，所述组合物包括溶剂和有机硅烷聚合物，所述有机硅烷聚合物是至少一种由化学式1和2表示的第一化合物的缩聚产物和至少一种化学式3〜5表示的第二化合物。

36. 发明授权

US07643355B2 Semiconductor memory device and method of inputting/outputting data 有权
标题翻译：半导体存储器件及其输入/输出方法
公开(公告)号：US07643355B2
公开(公告)日：2010-01-05
申请号：US11896722
申请日：2007-09-05
申请人： Joung-Yeal Kim , Jeong-Don Lim , Sung-Hoon Kim , Woo-Jin Lee
发明人： Joung-Yeal Kim , Jeong-Don Lim , Sung-Hoon Kim , Woo-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C2207/107
摘要： According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.
摘要翻译：根据示例实施例，半导体存储器件可以包括存储器芯，输入电路和/或输出电路。输入电路可以被配置为使用响应于在不同周期期间启用的输入控制信号而工作的锁存电路从第一数据产生第二数据。输入电路还可以被配置为向存储器核提供第二数据。第二数据可以具有2N次第一数据的比特数，其中N是正整数。输出电路可以被配置为使用响应于在不同周期期间启用的输出控制信号而工作的锁存电路从第三数据生成第四数据。输出电路还可以被配置为向数据输出引脚提供第四数据。第四数据可以具有第三数据的比特数的1/2N倍。还提供了一种输入/输出数据的方法。

37. 发明申请

US20050020301A1 Method for managing a schedule in a mobile communication terminal 审中-公开
标题翻译：用于在移动通信终端中管理日程表的方法
公开(公告)号：US20050020301A1
公开(公告)日：2005-01-27
申请号：US10653492
申请日：2003-09-02
申请人： Woo-Jin Lee
发明人： Woo-Jin Lee
IPC分类号： H04B1/40 , H04M1/725 , H04M1/00
CPC分类号： H04M1/72566
摘要： A method for managing a schedule using a mobile communication terminal, and a schedule management method based on contents of a schedule. A method for managing a schedule according to a level of importance according to a level of in a mobile communication terminal includes the steps of: a) determining whether a present time matches an alarm time for schedule notification; b) if the present time matches the alarm time for schedule notification, displaying contents of the schedule; c) determining whether a scheduled time of a schedule item contained in the schedule has passed; d) if the scheduled time of the schedule item has passed, determining importance of the schedule item; and e) if the schedule item is of low-level importance, deleting contents of the schedule item.
摘要翻译：一种使用移动通信终端管理日程表的方法，以及基于日程表的内容的日程管理方法。根据移动通信终端中的等级，根据重要程度来管理日程表的方法包括以下步骤：a）确定当前时间是否与调度通知的闹钟时间相匹配; b）如果当前时间与计划通知的闹钟时间相匹配，则显示时间表的内容; c）确定包含在时间表中的时间表项目的预定时间是否已经过去; d）如果计划项目的预定时间已过，则确定计划项目的重要性; 和e）如果调度项目是低级重要性，则删除调度项目的内容。

38. 发明授权

US09396988B2 Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns 有权
标题翻译：使用衬里层制造半导体器件以避免损坏底层图案的方法
公开(公告)号：US09396988B2
公开(公告)日：2016-07-19
申请号：US14703556
申请日：2015-05-04
申请人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
发明人： Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
IPC分类号： H01L21/02 , H01L21/311 , H01L21/70 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76843 , H01L2221/1063
摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
摘要翻译：一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案，衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

39. 发明授权

US09291899B2 Resist underlayer composition and method of manufacturing semiconductor integrated circuit device using the same 有权
标题翻译：抗蚀剂底层组合物和使用其制造半导体集成电路器件的方法
公开(公告)号：US09291899B2
公开(公告)日：2016-03-22
申请号：US12654737
申请日：2009-12-30
申请人： Hyeon-Mo Cho , Sang-Kyun Kim , Chang-Soo Woo , Mi-Young Kim , Sang-Ran Koh , Hui-Chan Yun , Woo-Jin Lee , Jong-Seob Kim
发明人： Hyeon-Mo Cho , Sang-Kyun Kim , Chang-Soo Woo , Mi-Young Kim , Sang-Ran Koh , Hui-Chan Yun , Woo-Jin Lee , Jong-Seob Kim
IPC分类号： G03F7/075 , G03F7/09 , G03F7/11 , G03F7/30 , G03F7/36 , C08G77/50 , C08G77/52 , C08K5/00 , C08L83/04 , C08L83/14 , C09D183/04 , C09D183/14 , C08G77/12 , C08G77/14 , C08G77/16 , C08G77/18 , C08G77/20 , C08G77/24 , C08G77/26 , C08G77/00
CPC分类号： G03F7/0752 , C08G77/12 , C08G77/14 , C08G77/16 , C08G77/18 , C08G77/20 , C08G77/24 , C08G77/26 , C08G77/50 , C08G77/52 , C08G77/70 , C08K5/0008 , C08L83/04 , C08L83/14 , C09D183/04 , C09D183/14 , G03F7/0757 , G03F7/09 , G03F7/091 , G03F7/094 , G03F7/11 , G03F7/30 , G03F7/36
摘要： A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the composition including a solvent and an organosilane polymer, the organosilane polymer being a condensation polymerization product of at least one first compound represented by Chemical Formulae 1 and 2 and at least one second compound represented by Chemical Formulae 3 to 5.
摘要翻译：抗蚀剂下层组合物和半导体集成电路器件的制造方法，所述组合物包括溶剂和有机硅烷聚合物，所述有机硅烷聚合物是至少一种由化学式1和2表示的第一化合物的缩聚产物和至少一种化学式3〜5表示的第二化合物。

40. 发明申请

US20100291713A1 METHOD OF FORMING HIGHLY CONFORMAL AMORPHOUS CARBON LAYER 有权
标题翻译：形成高度一致的非晶碳层的方法
公开(公告)号：US20100291713A1
公开(公告)日：2010-11-18
申请号：US12467017
申请日：2009-05-15
申请人： Woo-Jin Lee , Atsuki Fukazawa
发明人： Woo-Jin Lee , Atsuki Fukazawa
IPC分类号： H01L21/66
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/02274 , H01L21/0337
摘要： A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate,
摘要翻译：在半导体衬底的不规则表面上形成共形无定形氢化碳层的方法包括：使含烃前体气化; 将蒸发的前体和氩气引入其中放置半导体衬底的CVD反应室; 通过等离子体CVD在半导体衬底的不规则表面上沉积共形无定形氢化碳层; 并控制沉积的共形无定形氢化碳层的共形比的沉积。控制包括（a）将保形无定形氢化碳层的台阶覆盖率调整为基板温度的函数为约30％或更高，和（b）调整共形无定形氢化碳层的共形比为约0.9至约 1.1作为RF功率和/或氩气流量的函数，

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