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31. 发明授权

US08649419B2 Method and apparatus for input signal offset compensation 有权
标题翻译：用于输入信号偏移补偿的方法和装置
公开(公告)号：US08649419B2
公开(公告)日：2014-02-11
申请号：US13323492
申请日：2011-12-12
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H04B1/38
CPC分类号： H03M1/0607 , H03K17/005 , H03M1/361
摘要： A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result.
摘要翻译：提供了一种用于比较器偏移的补偿器的方法。测量通过比较器的比较器的第一信号到比较器的第一输出端的第一传播延迟以及通过比较器到比较器的第二输出端的第二信号的第二传播延迟。然后比较第一和第二传播延迟以产生比较结果，并且至少部分地基于比较结果来调整比较器以补偿输入电压偏移。

32. 发明申请

US20130148702A1 METHOD AND APPARATUS FOR INPUT SIGNAL OFFSET COMPENSATION 有权
标题翻译：输入信号偏移补偿的方法和装置
公开(公告)号：US20130148702A1
公开(公告)日：2013-06-13
申请号：US13323492
申请日：2011-12-12
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H04B1/38 , H04L27/01 , H03L7/00
CPC分类号： H03M1/0607 , H03K17/005 , H03M1/361
摘要： A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result.
摘要翻译：提供了一种用于比较器偏移的补偿器的方法。测量通过比较器的比较器的第一信号到比较器的第一输出端的第一传播延迟以及通过比较器到比较器的第二输出端的第二信号的第二传播延迟。然后比较第一和第二传播延迟以产生比较结果，并且至少部分地基于比较结果来调整比较器以补偿输入电压偏移。

33. 发明申请

US20130015990A1 TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH 审中-公开
标题翻译：跟踪和保持架构与可控带宽
公开(公告)号：US20130015990A1
公开(公告)日：2013-01-17
申请号：US13551950
申请日：2012-07-18
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/10
CPC分类号： H03M1/08 , H03M1/1215
摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
摘要翻译：到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。这里，提供使用采样开关（其改变采样开关的导通电阻）的栅极电压的变化来改变T / H电路的带宽以便精确匹配带宽的T / H电路架构。

34. 发明申请

US20120280720A1 INTRA-PAIR SKEW CANCELLATION TECHNIQUE FOR DIFFERENTIAL SIGNALING 有权
标题翻译：用于差分信号的内部消除噪声技术（INTRA-PAIR SKEW CANCELLATION TECHNIQUE FOR DIFFERENTIAL SIGNALING）
公开(公告)号：US20120280720A1
公开(公告)日：2012-11-08
申请号：US13100965
申请日：2011-05-04
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K5/22
CPC分类号： H03K5/003 , H04L25/0276
摘要： A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.
摘要翻译：提供了一种用于偏差校正差分信号的方法。测量差分信号的共模电压和差分信号的共模电压的平均值。确定差分信号的第一和第二部分之间的差异，并且从共模电压和平均值导出偏斜消除信息。然后可以将偏斜消息信息与差异组合以对差分信号进行去偏移。

35. 发明申请

US20120092199A1 PIPELINED ADC HAVING A THREE-LEVEL DAC ELEMENTS 有权
标题翻译：具有三级DAC元件的管道ADC
公开(公告)号：US20120092199A1
公开(公告)日：2012-04-19
申请号：US12904688
申请日：2010-10-14
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： H03M1/00 , H03M1/66
CPC分类号： H03M1/069 , H03M1/44
摘要： In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used.
摘要翻译：在传统的流水线模数转换器（ADC）中，通常在使用两态开关或段的ADC级中采用数模转换器（DAC）。这种安排的一个问题是，对于每个DAC状态，每个DAC开关都有来自其当前源的噪声贡献。然而，这里使用DAC，其使用三态DAC开关，这减少了DAC开关的电流源的噪声贡献，并减少了使用的面积。

36. 发明申请

US20120062402A1 MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING 有权
标题翻译：多功能放大器，具有降低玻璃化
公开(公告)号：US20120062402A1
公开(公告)日：2012-03-15
申请号：US12880311
申请日：2010-09-13
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03M1/00
CPC分类号： H03M1/0872 , H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
摘要翻译：在使用以小于50％工作周期工作的放大器的许多应用中，减少数量放大器以降低功耗将是有利的。这里，提供了一种放大器，其被时分复用以容纳多个数据路径。此外，在该放大器的输出端子处提供复位电路或复位机构，以短暂地输出端子短路，以防止可能由数据路径之间切换引起的毛刺。

37. 发明申请

US20120044004A1 TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH 有权
标题翻译：跟踪和保持架构与可控带宽
公开(公告)号：US20120044004A1
公开(公告)日：2012-02-23
申请号：US12857674
申请日：2010-08-17
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03L7/00
CPC分类号： H03M1/08 , H03M1/1215
摘要： To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
摘要翻译：到目前为止，时间交织（TI）模数转换器（ADC）中的带宽不匹配已被大大忽略，因为通过数字后处理（即有限脉冲响应滤波器）执行带宽不匹配的补偿。然而，数字后处理的滞后在高速系统中是禁止的，表明需要盲目错配补偿。即使使用盲带宽失配估计，TI ADC内的跟踪保持（T / H）电路的滤波特性的调整也是困难的。这里，提供了使用采样开关的栅极电压的变化（其改变采样开关的“开”电阻）的T / H电路架构，以改变T / H电路的带宽，以便精确匹配带宽。

38. 发明申请

US20110018750A1 ERROR CORRECTION METHOD AND APPARATUS 有权
标题翻译：错误校正方法和装置
公开(公告)号：US20110018750A1
公开(公告)日：2011-01-27
申请号：US12896603
申请日：2010-10-01
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03M1/06 , H03L7/06 , H03M1/66
CPC分类号： G05F3/265
摘要： A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.
摘要翻译：提供开关电流源。开关电流源通常由晶体管和电阻组成，源极具有高输出阻抗。与切换的电流源一起包括纠错晶体管和电阻器，其协作以通过偏置晶体管馈送电流以校正通常由开关电流源内的晶体管的电流增益或电流导致的误差。然而，为了实现这一点，电阻器被选择为具有足够大的值，使得来自误差校正晶体管的电流流过偏置晶体管。

39. 发明申请

US20090219059A1 TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION 有权
标题翻译：具有低失真的跟踪和保持电路
公开(公告)号：US20090219059A1
公开(公告)日：2009-09-03
申请号：US12393164
申请日：2009-02-26
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： G11C27/02
CPC分类号： G11C27/026 , H03M1/0624 , H03M1/1245
摘要： A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant.
摘要翻译：提供跟踪和保持电路。该跟踪和保持电路适于跟踪模拟输入信号并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。优选地，跟踪和保持电路包括双向电流源，其通过第一输出节点和第二输出节点来源和吸收电流，单位增益放大器耦合到双向的第一和第二输出节点电流源，并且接收模拟输入信号，耦合到单位增益放大器的输出的电阻器和耦合在电阻器和地之间的电容器。然而，感兴趣的是双向电流源，其包括适于接收轨道信号和保持信号并且耦合到第一和第二输出节点的差分输入电路以及耦合到差分输入电路。 RC网络接收模拟输入信号，并被缩放以改变零点的位置以减小采样时刻的信号依赖性。

40. 发明申请

US20080219380A1 Data Encoding in a Clocked Data Interface 有权
标题翻译：时钟数据接口中的数据编码
公开(公告)号：US20080219380A1
公开(公告)日：2008-09-11
申请号：US11696486
申请日：2007-04-04
申请人： Robert F. Payne , Richard M. Prentice
发明人： Robert F. Payne , Richard M. Prentice
IPC分类号： H04L25/49
CPC分类号： H04L7/0008 , H04L7/04
摘要： One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.
摘要翻译：本发明的一个实施例包括数据传输系统。该系统包括在至少一条数据线上提供多个数据位的数据发送器。数据发射机包括提供与用于锁存多个数据位的定时相关联的时钟信号的时钟和被配置为在时钟信号中对与数据传输系统相关联的错误数据进行编码的数据编码器。

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