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31. 发明授权

US6066180A Automatic generation of phase shift masks using net coloring 有权
标题翻译：使用净色自动生成相移掩模
公开(公告)号：US6066180A
公开(公告)日：2000-05-23
申请号：US268414
申请日：1999-03-15
申请人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
发明人： Young O. Kim , Mark A. Lavin , Lars W. Liebmann , Glenwood S. Weinert
IPC分类号： G03F1/08 , G06F17/50 , H01L21/027 , G06K9/00
CPC分类号： G06F17/5068
摘要： According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.
摘要翻译：根据优选实施例，提供了一种用于自动着色VLSI设计元件以便为元件分配二进制特性的方法。优选的方法特别适用于从VLSI CAD数据集产生相移掩模设计。首选方法使用净色来自动生成彩色元素的数据集。优选的方法不依赖于操作元件的顺序。优选的方法具有能够自动检测阻止VLSI设计被最佳着色的冲突的额外优点。优选的方法同样适用于具有嵌套组件和传统平面数据库的分层VLSI数据库。当应用分层数据库时，首选方法提供了元素着色，需要最少的数据平坦化。

32. 发明授权

US6057063A Phase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith 失效
标题翻译：相移掩模设计系统，相移掩模和用其制造的VLSI电路器件
公开(公告)号：US6057063A
公开(公告)日：2000-05-02
申请号：US824700
申请日：1997-04-14
申请人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
发明人： Lars W. Liebmann , Ioana C. Graur , Young O. Kim , Mark A. Lavin , Alfred K. Wong
IPC分类号： G03F1/00 , G06F17/50 , G03F9/00
CPC分类号： G06F17/5068 , G03F1/26
摘要： A process for creating and verifying a design of phase-shifted masks utilizing at least one phase shift region employing a computer-aided design system. A chip design is provided. A phase-shift mask design capable of producing the chip design is created. Features in a design of the phase-shifted mask that require phase shifting are located. Uncolored phase regions are created on opposite sides of the features. Proper phase termination of the phase regions is ensured based upon space constraints of a phase-shifted mask technique utilized. Phases are determined for the phase regions. Whether coloring errors and un-phase-shiftable design features exist is determined. Mask process specific overlaps and expansions are applied to the mask design to prepare designed data levels for mask manufacture. A residual phase edge image removal design is derived.
摘要翻译：利用采用计算机辅助设计系统的至少一个相移区域来创建和验证相移掩模的设计的过程。提供芯片设计。产生了能够产生芯片设计的相移掩模设计。定位需要相移的相移掩模设计中的特征。未着色的相位区域在特征的相对侧上创建。基于所采用的相移掩模技术的空间限制，确保相位区域的正确相位终止。确定相位区域的相位。是否存在着色误差和不相移设计特征。掩模过程特定的重叠和扩展被应用于掩模设计以准备用于掩模制造的设计的数据级。导出残留相边缘图像去除设计。

33. 发明授权

US5923563A Variable density fill shape generation 失效
标题翻译：可变密度填充形状生成
公开(公告)号：US5923563A
公开(公告)日：1999-07-13
申请号：US770925
申请日：1996-12-20
申请人： Mark A. Lavin , William C. Leipold
发明人： Mark A. Lavin , William C. Leipold
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： The present invention is directed to a method for adding fill shapes to a chip in a manner which accommodates a wide range of within-chip pattern density variations and provides a tight pattern density control (i) within a chip and (ii) from chip to chip. The present invention imposes a grid over a chip design pattern, wherein each section of the grid contains a portion of the chip design. A pattern density is then determined for each section of the grid, based on that portion of the chip design pattern which lies within the particular grid section. The results of the pattern density determination are used to determine where to place fill shapes in the chip design in order to increase a density value in each section of the grid to that of a target density value. The method and apparatus of the present invention provide a best fit approximation to the desired pattern density consistent with a set of layout rules for the level being patterned.
摘要翻译：本发明涉及一种用于以适合宽范围的片内图案密度变化的方式向芯片添加填充形状的方法，并且提供在芯片内的紧密图案密度控制（i）和（ii）从芯片到芯片。本发明在芯片设计图案上施加格栅，其中网格的每个部分包含芯片设计的一部分。然后，基于位于特定网格部分内的芯片设计图案部分，确定网格的每个部分的图案密度。使用图案密度确定的结果来确定在芯片设计中将填充形状放置在哪里，以便将网格的每个部分中的密度值增加到目标密度值的密度值。本发明的方法和装置提供与期望图案密度的最佳拟合近似，其与图案化级别的一组布局规则一致。

34. 发明授权

US5636133A Efficient generation of fill shapes for chips and packages 失效
标题翻译：有效地生成芯片和封装的填充形状
公开(公告)号：US5636133A
公开(公告)日：1997-06-03
申请号：US445447
申请日：1995-05-19
申请人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
发明人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
摘要翻译：修改芯片或封装设计的有效方法允许创建小形状而不会过度扩展设计数据。计算机程序采用计算机数据文件中的物理设计，并生成已添加填充形状的设计的修改版本。随后，当改进的设计被处理时，所得到的半导体芯片或封装将包含所添加的填充形状的物理图像，具有使局部图案密度更均匀并因此减少特征尺寸和形状的工艺引起的变化的效果。

35. 发明授权

US08073288B2 Rendering a mask using coarse mask representation 有权
标题翻译：使用粗糙掩码表示渲染掩模
公开(公告)号：US08073288B2
公开(公告)日：2011-12-06
申请号：US12015084
申请日：2008-01-16
申请人： Mark A. Lavin , Maharaj Mukherjee , Alan E. Rosenbluth
发明人： Mark A. Lavin , Maharaj Mukherjee , Alan E. Rosenbluth
IPC分类号： G06K9/20
CPC分类号： G03F7/705 , G03F1/36
摘要： A method, system and computer program product for rendering a mask are disclosed. A method of rendering a mask may comprise: providing an initial mask design for a photolithographic process, the initial mask design including polygons; initially rendering the initial mask design as a coarse mask representation in a pixel based image calculation; identifying an overhang portion; and rendering the overhang portion using a set of subpixels whose artifacts from spatial-localization lie outside a practical resolution of a pseudo lens having a numerical aperture larger than that of a projection lens used in the photolithographic process; and updating the initial rendering based on the overhang portion rendering.
摘要翻译：公开了一种用于渲染掩模的方法，系统和计算机程序产品。渲染掩模的方法可以包括：提供用于光刻工艺的初始掩模设计，初始掩模设计包括多边形; 最初在基于像素的图像计算中将初始掩模设计呈现为粗糙掩模表示; 识别突出部分; 并且使用一组子空间渲染悬伸部分，其中来自空间定位的伪像位于具有大于在光刻工艺中使用的投影透镜的数值孔径的假透镜的实际分辨率之外; 并基于突出部分呈现来更新初始呈现。

36. 发明授权

US07831941B2 CA resistance variability prediction methodology 有权
标题翻译： CA抗性变异性预测方法
公开(公告)号：US07831941B2
公开(公告)日：2010-11-09
申请号：US11968458
申请日：2008-01-02
申请人： Dureseti Chidambarrao , Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Rama N. Singh , Roger Y. Tsai
发明人： Dureseti Chidambarrao , Fook-Luen Heng , Mark A. Lavin , Jin-Fuw Lee , Rama N. Singh , Roger Y. Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
摘要翻译：一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

37. 发明授权

US07774737B2 Performance in model-based OPC engine utilizing efficient polygon pinning method 失效
公开(公告)号：US07774737B2
公开(公告)日：2010-08-10
申请号：US11756883
申请日：2007-06-01
申请人： Gregg M Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the located points of interest is computed, followed by determining a spatial relation between its vertices and the ROI. The vertices of the first polygon are then pinned to boundaries of and within the ROI such that a second polygon is formed on the ROI. The process is repeated for all vertices of the first polygon such that the second polygon is collapsed onto the ROI. This collapsed second polygon is then used to correct for optical proximity.

38. 发明授权

US07709967B2 Shapes-based migration of aluminum designs to copper damascene 失效
标题翻译：基于形状的铝设计迁移到铜镶嵌
公开(公告)号：US07709967B2
公开(公告)日：2010-05-04
申请号：US11837723
申请日：2007-08-13
申请人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
发明人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译：互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。互连结构包括具有电介质填充孔图案的镶嵌金属线。

39. 发明申请

US20080247633A1 SYSTEM FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM 审中-公开
标题翻译：用于生成一组用于光临近度校正算法的测试模式的系统
公开(公告)号：US20080247633A1
公开(公告)日：2008-10-09
申请号：US12117934
申请日：2008-05-09
申请人： David L DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： David L DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的系统。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

40. 发明授权

US07415695B2 System for search and analysis of systematic defects in integrated circuits 有权
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07415695B2
公开(公告)日：2008-08-19
申请号：US11748575
申请日：2007-05-15
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

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