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31. 发明申请

US20120092923A1 READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY 有权
标题翻译：阅读配置管理相位变化记忆
公开(公告)号：US20120092923A1
公开(公告)日：2012-04-19
申请号：US12905754
申请日：2010-10-15
申请人： Ferdinando Bedeschi , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Roberto Gastaldi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2211/5634 , G11C2213/54
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
摘要翻译：本文公开的主题涉及存储器件，更具体地涉及写入相变存储器的性能。

32. 发明授权

US4802166A Device for the verification of memory cells on the basis of the threshold drop obtainable during writing 失效
标题翻译：基于在写入期间可获得的阈值下降来验证存储器单元的装置
公开(公告)号：US4802166A
公开(公告)日：1989-01-31
申请号：US835059
申请日：1986-02-28
申请人： Giulio Casagrande , Roberto Gastaldi
发明人： Giulio Casagrande , Roberto Gastaldi
IPC分类号： G11C29/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C17/00 , G11C29/12 , G11C29/50
CPC分类号： G11C16/3459 , G11C16/3454 , G11C29/50 , G11C29/50004 , G06F2201/81 , G11C16/04
摘要： A comparator has two inputs, one controlled by a circuit branch including a written cell being examined and one controlled by another circuit branch including a virgin cell. In parallel with the latter is placed another reference cell controlled in an adjustable manner in such a way as to raise the threshold of the written cell which the device is able to discriminate and accept.
摘要翻译：比较器具有两个输入，一个由电路支路控制，该电路支路包括被检查的一个写入单元，另一个由包括一个原始单元的另一个电路支路控制。与后者并行放置另一参考单元以可调节的方式控制，以提高装置能够区分和接受的写入单元的阈值。

33. 发明授权

US06532171B2 Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units 有权
标题翻译：能够选择性地擦除多个元件存储器单元的非易失性半导体存储器
公开(公告)号：US06532171B2
公开(公告)日：2003-03-11
申请号：US09919789
申请日：2001-07-31
申请人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
发明人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1616
CPC分类号： G11C16/3431 , G11C16/16 , G11C16/34
摘要： A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.
摘要翻译：诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列形成包。具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

34. 发明授权

US4847811A Pre-charging circuit for word lines of a memory system, in particular with programmable cells 失效
标题翻译：对于存储器系统的字线，特别是可编程单元的字线的预充电电路
公开(公告)号：US4847811A
公开(公告)日：1989-07-11
申请号：US144696
申请日：1988-01-13
申请人： Roberto Gastaldi , Giulio Casagrande
发明人： Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C16/08
CPC分类号： G11C8/08 , G11C16/08
摘要： A voltage divider is placed between a supply terminal and ground and an intermediate node is connected to the word line to ensure a precharging voltage to the word line which is lower than the supply voltage. The voltage divider is characterized by a precharging transistor included in the voltage divider which has electrical and geometrical characteristics similar to those of the memory cells in such a manner as to adapt the precharging voltage to the characteristics of the cells.
摘要翻译：分压器放置在电源端子和地之间，中间节点连接到字线，以确保字线的预充电电压低于电源电压。分压器的特征在于包括在分压器中的预充电晶体管，其具有类似于存储器单元的电和几何特性，以使预充电电压适应电池的特性。

35. 发明授权

US07159284B2 Seat belt buckle, in particular for racing vehicles 有权
标题翻译：安全带扣，特别是赛车
公开(公告)号：US07159284B2
公开(公告)日：2007-01-09
申请号：US10935083
申请日：2004-09-08
申请人： Roberto Gastaldi
发明人： Roberto Gastaldi
IPC分类号： A44B11/25
CPC分类号： A44B11/2542 , Y10T24/45618 , Y10T24/45623
摘要： A seat belt buckle, in particular for racing vehicles, having: a casing defining at least one slot engageable by an end member of a strap of a seat belt for connection; a lock mechanism housed in the casing and for releasably retaining the end member; and a release lever fitted to the casing and movable, from a rest position, along a path lying in an actuating plane to release the lock mechanism from the end member, the release lever having an end projecting from the casing in the actuating plane as the release lever moves along the path. The buckle also has a lever guard portion fitted to the casing and having a lateral surface, an ideal extension of which in a direction perpendicular to the actuating plane surrounds the end of the release lever in the rest position.
摘要翻译：一种安全带扣，特别是用于赛车的安全带扣，具有：限定至少一个槽的壳体，该槽可由用于连接的安全带的带的端部构件接合; 锁定机构，其容纳在所述壳体中并且用于可释放地保持所述端部构件; 以及释放杆，其安装到所述壳体并且从静止位置沿着位于致动平面中的路径移动以从所述端部构件释放所述锁定机构，所述释放杆具有在所述致动平面中从所述壳体突出的端部，释放杆沿着路径移动。带扣还具有安装到壳体并具有侧表面的杠杆保护部分，其在垂直于致动平面的方向上的理想的延伸部围绕释放杆的在静止位置的端部。

36. 外观设计

USD515456S1 Buckle for safety belts 失效
公开(公告)号：USD515456S1
公开(公告)日：2006-02-21
申请号：US29212103
申请日：2004-08-25
申请人： Roberto Gastaldi
设计人： Roberto Gastaldi

37. 发明申请

US20050086778A1 Seat belt buckle, in particular for racing vehicles 有权
标题翻译：安全带扣，特别是赛车
公开(公告)号：US20050086778A1
公开(公告)日：2005-04-28
申请号：US10935083
申请日：2004-09-08
申请人： Roberto Gastaldi
发明人： Roberto Gastaldi
IPC分类号： A44B11/25
CPC分类号： A44B11/2542 , Y10T24/45618 , Y10T24/45623
摘要： A seat belt buckle, in particular for racing vehicles, having: a casing defining at least one slot engageable by an end member of a strap of a seat belt for connection; a lock mechanism housed in the casing and for releasably retaining the end member; and a release lever fitted to the casing and movable, from a rest position, along a path lying in an actuating plane to release the lock mechanism from the end member, the release lever having an end projecting from the casing in the actuating plane as the release lever moves along the path. The buckle also has a lever guard portion fitted to the casing and having a lateral surface, an ideal-extension of which in a direction perpendicular to the actuating plane surrounds the end of the release lever in the rest position.
摘要翻译：一种安全带扣，特别是用于赛车的安全带扣，具有：限定至少一个槽的壳体，该槽可由用于连接的安全带的带的端部构件接合; 锁定机构，其容纳在所述壳体中并且用于可释放地保持所述端部构件; 以及释放杆，其安装到所述壳体并且从静止位置沿着位于致动平面中的路径移动以从所述端部构件释放所述锁定机构，所述释放杆具有在所述致动平面中从所述壳体突出的端部，释放杆沿着路径移动。带扣还具有装配到壳体的杠杆保护部分，并且具有侧表面，在垂直于致动平面的方向上围绕释放杆的端部处于静止位置的理想延伸部分。

38. 发明授权

US06839818B2 Electrically modifiable, non-volatile, semiconductor memory which can keep a datum stored until an operation to modify the datum is completed 失效
标题翻译：完成可修改基准的操作之前可以保存数据的电可修改的非易失性半导体存储器
公开(公告)号：US06839818B2
公开(公告)日：2005-01-04
申请号：US10036088
申请日：2001-12-28
申请人： Roberto Gastaldi , Gianbattsista Lo Giudice , Marco Pasotti , Federico Pio
发明人： Roberto Gastaldi , Gianbattsista Lo Giudice , Marco Pasotti , Federico Pio
IPC分类号： G11C16/10 , G06F12/00
CPC分类号： G11C16/102
摘要： An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify the data held therein is characterized in that, for each user memory location, there is a corresponding pair of physical memory locations in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.
摘要翻译：一种可电气修改的非易失性半导体存储器，其包括多个用户存储器位置，其可以从存储器外部单独寻址以便读取和修改其中保存的数据，其特征在于，对于每个用户存储器位置，存储器中的对应物理存储器位置对，其替代地假设有效存储器位置和非活动存储器位置的功能，所述活动存储器位置包含预先写入的数据和非活动存储器位置可用于写入新的数据以替换以前写入的数据，以便在要求使用新数据替换以前的数据时，先前的数据保存在存储器中，直到新的数据被写入。

39. 发明授权

US5673221A Circuit and method for reading a memory cell that can store multiple bits of data 失效
标题翻译：用于读取可存储多个数据位的存储单元的电路和方法
公开(公告)号：US5673221A
公开(公告)日：1997-09-30
申请号：US592939
申请日：1996-01-29
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C16/04 , G11C11/56 , G11C16/02 , G11C17/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
摘要翻译：用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流。

40. 发明授权

US08325528B1 Multi-layer flash memory 有权
标题翻译：多层闪存
公开(公告)号：US08325528B1
公开(公告)日：2012-12-04
申请号：US12764054
申请日：2010-04-20
申请人： Alessandro Grossi , Anna Maria Conti , Roberto Gastaldi
发明人： Alessandro Grossi , Anna Maria Conti , Roberto Gastaldi
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11573 , H01L27/11578
摘要： Subject matter disclosed herein relates to a multi-layer memory, and more particularly to operating same.
摘要翻译：本文公开的主题涉及多层存储器，更具体地涉及其操作。

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