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31. 发明授权

US07960835B2 Fabrication of metal film stacks having improved bottom critical dimension 有权
标题翻译：具有改进的底部临界尺寸的金属膜堆叠的制造
公开(公告)号：US07960835B2
公开(公告)日：2011-06-14
申请号：US12435336
申请日：2009-05-04
申请人： Han-Hui Hsu , Ta-Hung Yang , Shih-Ping Hong , Ming-Tsung Wu , An-Chi Wei , Ching-Hsiung Li , Kuo-Liang Wei
发明人： Han-Hui Hsu , Ta-Hung Yang , Shih-Ping Hong , Ming-Tsung Wu , An-Chi Wei , Ching-Hsiung Li , Kuo-Liang Wei
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/0276 , H01L21/32139 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.
摘要翻译：描述了制造金属膜堆叠的方法，其减少或消除光刻不对准的不利影响。通过去除底部氮化钛屏障来增加底部临界尺寸。

32. 发明申请

US20100276807A1 FABRICATION OF METAL FILM STACKS HAVING IMPROVED BOTTOM CRITICAL DIMENSION 有权
标题翻译：具有改进的底部关键尺寸的金属膜堆的制造
公开(公告)号：US20100276807A1
公开(公告)日：2010-11-04
申请号：US12435336
申请日：2009-05-04
申请人： Han-Hui Hsu , Ta-Hung Yang , Shih-Ping Hong , Ming-Tsung Wu , An-Chi Wei , Ching-Hsiung Li , Kuo-Liang Wei
发明人： Han-Hui Hsu , Ta-Hung Yang , Shih-Ping Hong , Ming-Tsung Wu , An-Chi Wei , Ching-Hsiung Li , Kuo-Liang Wei
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/0276 , H01L21/32139 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.
摘要翻译：描述了制造金属膜堆叠的方法，其减少或消除光刻不对准的不利影响。通过去除底部氮化钛屏障来增加底部临界尺寸。

33. 发明申请

US20070032060A1 Method for forming conductive wiring and interconnects 审中-公开
标题翻译：形成导电布线和互连的方法
公开(公告)号：US20070032060A1
公开(公告)日：2007-02-08
申请号：US11197822
申请日：2005-08-05
申请人： Ta-Hung Yang
发明人： Ta-Hung Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76885 , H01L21/76895
摘要： A method for forming conductive wiring is provided. First, a material layer having at least a trench is provided. A conductive material layer is formed on the material layer to fill the trench and cover the top surface of the material layer. A patterned mask layer is formed on the conductive material layer. The conductive material layer not covered by the patterned mask layer is removed. After that, the patterned mask layer is removed.
摘要翻译：提供一种形成导电布线的方法。首先，提供具有至少沟槽的材料层。在材料层上形成导电材料层以填充沟槽并覆盖材料层的顶表面。在导电材料层上形成图案化掩模层。除去未被图案化掩模层覆盖的导电材料层。之后，去除图案化的掩模层。

34. 发明申请

US20070145005A1 CONTROLLING SYSTEM AND METHOD FOR OPERATING THE SAME 有权
标题翻译：控制系统及其操作方法
公开(公告)号：US20070145005A1
公开(公告)日：2007-06-28
申请号：US11306417
申请日：2005-12-28
申请人： Chao-Lung Lo , Ta-Hung Yang
发明人： Chao-Lung Lo , Ta-Hung Yang
IPC分类号： H01L21/461 , G01L21/30 , H01L21/302 , C23F1/00
CPC分类号： H01L21/0273 , G03F7/40 , H01L22/12
摘要： The invention is directed to a method for controlling a critical dimension of a patterned photoresist layer. The method comprises steps of measuring a critical dimension of a raised pattern in a patterned photoresist layer after a photolithography process is performed on the photoresist layer. A determining process is performed to determine whether the critical dimension is within a critical dimension control limit range, wherein the critical dimension control limit range has a upper control limit and a lower control limit. An adjusting process is performed when the critical dimension is not within the critical dimension control limit range. When the critical dimension is smaller than the lower control limit, a photoresist reflow process is performed. When the critical dimension is larger than the upper control limit a photoresist trimming process is performed.
摘要翻译：本发明涉及一种用于控制图案化光致抗蚀剂层的临界尺寸的方法。该方法包括以下步骤：在对光致抗蚀剂层进行光刻工艺之后测量图案化光致抗蚀剂层中的凸起图案的临界尺寸。执行确定过程以确定临界尺寸是否在临界尺寸控制极限范围内，其中临界尺寸控制限制范围具有上控制极限和较低控制极限。当临界尺寸不在关键尺寸控制限制范围内时，执行调整过程。当临界尺寸小于较低控制极限时，进行光致抗蚀剂回流工艺。当临界尺寸大于上限值时，进行光刻胶修整处理。

35. 发明申请

US20070054486A1 METHOD FOR FORMING OPENING 审中-公开
标题翻译：形成开放的方法
公开(公告)号：US20070054486A1
公开(公告)日：2007-03-08
申请号：US11162277
申请日：2005-09-05
申请人： Ta-Hung Yang
发明人： Ta-Hung Yang
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/76807
摘要： A method for forming an opening. The method comprises steps of providing a substrate having at least one element structure formed thereon and then forming a dielectric layer over the substrate to cover the element structure. A patterned metal silicide layer is formed on the dielectric layer and then the dielectric layer is etched to form at least one opening by using the patterned metal silicide layer as an etching mask, wherein the opening exposes the corresponding element structure.
摘要翻译：一种形成开口的方法。该方法包括提供具有形成在其上的至少一个元件结构的衬底，然后在衬底上形成覆盖元件结构的电介质层的步骤。在电介质层上形成图案化的金属硅化物层，然后通过使用图案化的金属硅化物层作为蚀刻掩模来蚀刻介电层以形成至少一个开口，其中开口暴露相应的元件结构。

36. 发明授权

US06875659B2 Methods of code programming a mask ROM 有权
标题翻译：掩码ROM代码编程方法
公开(公告)号：US06875659B2
公开(公告)日：2005-04-05
申请号：US10614698
申请日：2003-07-03
申请人： Ta-Hung Yang , Ching-Yu Chang
发明人： Ta-Hung Yang , Ching-Yu Chang
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126
摘要： A method of code programming a mask read only memory (ROM) is disclosed. According to the method, a first photoresist layer is formed over word lines and a gate oxide layer of a substrate already having implanted bit lines. The first photoresist layer is patterned to develop pre-code openings over all of the memory cells, which correspond to intersecting word and bit lines. The first photoresist layer is then hardened using either a treatment implant or a treatment plasma. Subsequently, a second photoresist layer is formed over the first photoresist layer and patterned to develop real-code openings over memory cells which are actually to be coded with a logic “0” value. Each memory cell to be coded is then implanted with implants passing through the pre-code openings and the real code openings and into the memory cell.
摘要翻译：公开了一种代码编程掩模只读存储器（ROM）的方法。根据该方法，在字线和具有注入位线的衬底的栅极氧化物层上形成第一光致抗蚀剂层。图案化第一光致抗蚀剂层以在对应于相交字和位线的所有存储单元上形成预编码开口。然后使用处理植入物或处理等离子体硬化第一光致抗蚀剂层。随后，在第一光致抗蚀剂层上形成第二光致抗蚀剂层，并将其图案化以在实际上以逻辑“0”值编码的存储器单元上形成实际代码开口。然后，将通过预代码开口和实际代码开口的植入物植入待编码的每个存储单元并进入存储单元。

37. 发明授权

US06799152B1 Critical dimension statistical process control in semiconductor fabrication 有权
标题翻译：半导体制造中的关键维度统计过程控制
公开(公告)号：US06799152B1
公开(公告)日：2004-09-28
申请号：US10206268
申请日：2002-07-26
申请人： Chih-Ping Chen , Shao-Chung Hsu , De-Chuan Liu , Jung-Kuei Lu , Cheng-Yi Lin , Ta-Hung Yang , Hsin-Cheng Liu , Mao-I Ting , Yih-Cheng Shih
发明人： Chih-Ping Chen , Shao-Chung Hsu , De-Chuan Liu , Jung-Kuei Lu , Cheng-Yi Lin , Ta-Hung Yang , Hsin-Cheng Liu , Mao-I Ting , Yih-Cheng Shih
IPC分类号： G06F1750
CPC分类号： G06F17/50 , G06F2217/10 , G07C3/146
摘要： The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.
摘要翻译：本发明提供了一种用于分析在集成电路制造期间发生的工艺变化的方法。针对集成电路制造过程的每个层收集关键尺寸数据一段时间，并且计算指示集成电路制造过程的每层的临界尺寸数据的变化的移位指示器。还针对在集成电路制造工艺的每个层中使用的每个机器计算机器漂移显着性指标，并且定义了集成电路制造工艺的每一层的平均值的最大偏移。移位指示器，平均值的最大偏移和机器漂移显着性指示器用于确定集成电路制造过程的每个层的关键尺寸的至少一个可能的变化原因。

38. 发明授权

US07648921B2 Method of forming dielectric layer 有权
标题翻译：形成介电层的方法
公开(公告)号：US07648921B2
公开(公告)日：2010-01-19
申请号：US11534583
申请日：2006-09-22
申请人： Hsu-Sheng Yu , Shing-Ann Lo , Ta-Hung Yang
发明人： Hsu-Sheng Yu , Shing-Ann Lo , Ta-Hung Yang
IPC分类号： H01L21/469
CPC分类号： H01L21/76837
摘要： A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.
摘要翻译：提供一种形成电介质层的方法。在其上形成有金属层的基板上形成第一介电层。第一电介质层包括在两个相邻的金属层之间的空间中的突出端和在突出端下方的空隙。部分地去除第一介电层以切断突出端并露出空隙，因此形成开口。在电介质层上形成第二电介质层以填满开口。

39. 发明授权

US07632616B2 Controlling system and method for operating the same 有权
标题翻译：控制系统及操作方法
公开(公告)号：US07632616B2
公开(公告)日：2009-12-15
申请号：US11306417
申请日：2005-12-28
申请人： Chao-Lung Lo , Ta-Hung Yang
发明人： Chao-Lung Lo , Ta-Hung Yang
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L21/0273 , G03F7/40 , H01L22/12
摘要： The invention is directed to a method for controlling a critical dimension of a patterned photoresist layer. The method comprises steps of measuring a critical dimension of a raised pattern in a patterned photoresist layer after a photolithography process is performed on the photoresist layer. A determining process is performed to determine whether the critical dimension is within a critical dimension control limit range, wherein the critical dimension control limit range has a upper control limit and a lower control limit. An adjusting process is performed when the critical dimension is not within the critical dimension control limit range. When the critical dimension is smaller than the lower control limit, a photoresist reflow process is performed. When the critical dimension is larger than the upper control limit a photoresist trimming process is performed.
摘要翻译：本发明涉及一种用于控制图案化光致抗蚀剂层的临界尺寸的方法。该方法包括以下步骤：在对光致抗蚀剂层进行光刻工艺之后测量图案化光致抗蚀剂层中的凸起图案的临界尺寸。执行确定过程以确定临界尺寸是否在临界尺寸控制极限范围内，其中临界尺寸控制限制范围具有上控制极限和较低控制极限。当临界尺寸不在关键尺寸控制限制范围内时，执行调整过程。当临界尺寸小于较低控制极限时，进行光致抗蚀剂回流工艺。当临界尺寸大于上限值时，进行光刻胶修整处理。

40. 发明申请

US20080305635A1 METHOD FOR FABRICATING A PATTERN 有权
标题翻译：用于制作图案的方法
公开(公告)号：US20080305635A1
公开(公告)日：2008-12-11
申请号：US11759622
申请日：2007-06-07
申请人： Shih-Chang Tsai , Chun-Hung Lee , Ming-Cheng Deng , Ta-Hung Yang
发明人： Shih-Chang Tsai , Chun-Hung Lee , Ming-Cheng Deng , Ta-Hung Yang
IPC分类号： H01L21/311 , H01L21/31
CPC分类号： H01L21/0337
摘要： A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask.
摘要翻译：提供了一种制造图案的方法。首先，提供材料层，其中形成图案化的硬掩模层。间隔物沉积在图案化的硬掩模层的侧壁上。然后，去除图案化的硬掩模层，并且在相邻间隔件之间形成开口。然后，通过使用间隔物作为掩模，去除材料层的一部分以形成图案化的材料层。

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