专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20070215224A1 MICRO-ELECTRO-MECHANICAL VALVES AND PUMPS AND METHODS OF FABRICATING SAME 有权
标题翻译：微机电阀和泵及其制造方法
公开(公告)号：US20070215224A1
公开(公告)日：2007-09-20
申请号：US11276772
申请日：2006-03-14
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： F15C1/06
CPC分类号： F15C1/06 , F04B43/043 , F15C5/00 , F16K99/0001 , F16K99/0015 , F16K99/0051 , F16K2099/0074 , F16K2099/0094 , Y10T29/49236 , Y10T29/49412 , Y10T137/2224
摘要： Micro-valves and micro-pumps and methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the micro-pumps is accomplished by applying electrostatic forces to the electrically conductive diaphragms.
摘要翻译：微型阀门和微型泵以及制造微型阀门和微型泵的方法。微型阀和微型泵包括由导电纳米纤维制成的导电隔膜。通过微型阀的流体流动和微型泵的泵送作用是通过将静电力施加到导电隔膜来实现的。

32. 发明申请

US20070207604A1 WIRING PATERNS FORMED BY SELECTIVE METAL PLATING 失效
标题翻译：通过选择性金属镀层形成的接线
公开(公告)号：US20070207604A1
公开(公告)日：2007-09-06
申请号：US11745610
申请日：2007-05-08
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/3205
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
摘要翻译：使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

33. 发明申请

US20070123028A1 METHODS OF FORMING LOW-K DIELECTRIC LAYERS CONTAINING CARBON NANOSTRUCTURES 有权
标题翻译：形成含有碳纳米结构的低K电介质层的方法
公开(公告)号：US20070123028A1
公开(公告)日：2007-05-31
申请号：US11670778
申请日：2007-02-02
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/4763
CPC分类号： H01L21/02115 , B82Y10/00 , H01L21/02282 , H01L21/3146 , H01L21/3185 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76831 , H01L21/76888 , H01L2221/1047
摘要： Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.
摘要翻译：形成用于制造半导体器件的低k电介质层并使用低k电介质材料制造半导体结构的方法。低k介电材料包括碳纳米结构，如碳纳米管或碳棒球，其特征在于绝缘电子状态。碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。将碳纳米结构转化为绝缘电子态的一种方法是氟化。

34. 发明申请

US20070105319A1 PATTERN DENSITY CONTROL USING EDGE PRINTING PROCESSES 有权
标题翻译：使用边缘印刷工艺的图案密度控制
公开(公告)号：US20070105319A1
公开(公告)日：2007-05-10
申请号：US11163968
申请日：2005-11-04
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L27/1052 , Y10S438/95
摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.
摘要翻译：一种结构制造方法。该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。接下来，提供实际结构，其包括（i）与设计基板相对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层层。接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

35. 发明申请

US20070085156A1 PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES 失效
标题翻译：被动电气测试加速和电压测量装置
公开(公告)号：US20070085156A1
公开(公告)日：2007-04-19
申请号：US11161181
申请日：2005-10-13
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Leah Pastel
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Leah Pastel
IPC分类号： H01L29/84
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口上，并与导电接触到所述纳米管。

36. 发明申请

US20070066009A1 SIDEWALL IMAGE TRANSFER (SIT) TECHNOLOGIES 失效
标题翻译： SIDEWALL图像传输（SIT）技术
公开(公告)号：US20070066009A1
公开(公告)日：2007-03-22
申请号：US11162662
申请日：2005-09-19
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Kirk Peterson
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Kirk Peterson
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132
摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.
摘要翻译：一种结构制造方法。该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。然后，定位区域缩进。然后，在结构的暴露于环境的表面上形成保形层。然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。然后，去除封盖区域，以将定位区域暴露于周围环境。然后，移除定位区域，以将存储区域暴露于周围环境。然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

37. 发明申请

US20070051237A1 CARBON NANOTUBES AS LOW VOLTAGE FIELD EMISSION SOURCES FOR PARTICLE PRECIPITATORS 失效
标题翻译：碳纳米管作为颗粒预处理器的低电压场发射源
公开(公告)号：US20070051237A1
公开(公告)日：2007-03-08
申请号：US11161220
申请日：2005-07-27
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： B03C3/41 , B03C3/60
CPC分类号： B03C3/41 , B03C3/60 , B03C2201/10 , Y10S977/742
摘要： An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube.
摘要翻译：空气颗粒除尘器和空气过滤方法包括壳体单元; 住房单元中的第一个导体; 壳体单元中的第二导体; 和在第二导体上生长的碳纳米管。优选地，第一导体与第二导体相对定位。空气粒子除尘器还包括适于向壳体单元施加电场的电场源。此外，碳纳米管适于使壳体单元中的气体电离，其中电离气体对位于壳体单元中的气体微粒进行充电，并且其中第一导体适于捕集带电气体微粒。空气颗粒除尘器还可以包括在碳纳米管上的金属层。

38. 发明申请

US20070048879A1 Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers 有权
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US20070048879A1
公开(公告)日：2007-03-01
申请号：US11552771
申请日：2006-10-25
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

39. 发明申请

US20060226480A1 METHOD FOR FABRICATING OXYGEN-IMPLANTED SILICON ON INSULATION TYPE SEMICONDUCTOR AND SEMICONDUCTOR FORMED THEREFROM 失效
标题翻译：在绝缘型半导体上制造氧化硅的方法及其形成的半导体
公开(公告)号：US20060226480A1
公开(公告)日：2006-10-12
申请号：US10907565
申请日：2005-04-06
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Larry Nesbit
IPC分类号： H01L27/12 , H01L21/76
CPC分类号： H01L21/76267 , H01L21/76243 , H01L21/76281 , H01L21/76283
摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.
摘要翻译：本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

40. 发明申请

US20060172547A1 IMPLANTATION OF GATE REGIONS IN SEMICONDUCTOR DEVICE FABRICATION 失效
标题翻译：在半导体器件制造中的栅极区域的植入
公开(公告)号：US20060172547A1
公开(公告)日：2006-08-03
申请号：US10905977
申请日：2005-01-28
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L21/302 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/0273 , H01L21/266 , H01L21/28035 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.
摘要翻译：一种注入栅极区域的方法，其基本上不注入将在其后形成源极/漏极区域的半导体层的区域。该方法包括以下步骤：（i）在半导体层上提供（i）半导体层，（ii）栅极电介质层，（iii）栅极介电层上的栅极区域，其中栅极区域与半导体层由栅介质层; （b）在栅介质层和栅极区上形成抗蚀剂层; （c）基本上直接在栅极区域上方去除抗蚀剂层的盖部分，而不去除抗蚀剂层的其余部分; 和（d）基本上不注入半导体层来注入栅极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式