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31. 发明授权

US07786583B2 Integrated circuit chip utilizing oriented carbon nanotube conductive layers 失效
标题翻译：集成电路芯片利用定向碳纳米管导电层
公开(公告)号：US07786583B2
公开(公告)日：2010-08-31
申请号：US11924894
申请日：2007-10-26
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H Mitchell
IPC分类号： H01L23/48
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

32. 发明授权

US07699996B2 Sidewall image transfer processes for forming multiple line-widths 失效
标题翻译：用于形成多个线宽的侧壁图像传输过程
公开(公告)号：US07699996B2
公开(公告)日：2010-04-20
申请号：US11680204
申请日：2007-02-28
申请人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III
IPC分类号： H01B13/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD
摘要翻译：同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。然后，对SIT层进行图案化，形成SIT区域。然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。所述图案化包括光刻工艺。退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维度W2和第二维度W3，其中CD

33. 发明授权

US07674674B2 Method of forming a dual gated FinFET gain cell 有权
标题翻译：形成双门控FinFET增益单元的方法
公开(公告)号：US07674674B2
公开(公告)日：2010-03-09
申请号：US12144139
申请日：2008-06-23
申请人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Mark Eliot Masters , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Mark Eliot Masters , Peter H. Mitchell
IPC分类号： H01L21/8244
CPC分类号： H01L27/108 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.
摘要翻译：用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。第一栅电极与存储装置电耦合。第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。当门控时，电流的大小取决于存储设备存储的电量。

34. 发明授权

US07629192B2 Passive electrically testable acceleration and voltage measurement devices 失效
标题翻译：被动电气可测加速度和电压测量装置
公开(公告)号：US07629192B2
公开(公告)日：2009-12-08
申请号：US11161181
申请日：2005-10-13
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Leah Marie Pfeifer Pastel
IPC分类号： H01L21/00
CPC分类号： G01P15/0802 , B82Y15/00 , G01P15/06 , G01P15/0891 , G01P15/135 , H01H1/0094 , H01H35/14
摘要： Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.
摘要翻译：加速度和电压测量装置以及制造加速度和电压测量装置的方法。所述加速和电压测量装置包括在第一绝缘层的顶表面上的导电板; 在所述导电板的顶表面上的第二绝缘层，所述板的顶表面暴露在所述第二绝缘层的开口中; 导电纳米管悬挂在开口处，并且与纳米管的导电接触。

35. 发明授权

US07505110B2 Micro-electro-mechanical valves and pumps 有权
标题翻译：微机电阀门和泵
公开(公告)号：US07505110B2
公开(公告)日：2009-03-17
申请号：US11276772
申请日：2006-03-14
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： F16K31/02
CPC分类号： F15C1/06 , F04B43/043 , F15C5/00 , F16K99/0001 , F16K99/0015 , F16K99/0051 , F16K2099/0074 , F16K2099/0094 , Y10T29/49236 , Y10T29/49412 , Y10T137/2224
摘要： Methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps that are fabricated include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the micro-pumps is accomplished by applying electrostatic forces to the electrically conductive diaphragms.
摘要翻译：制造微型阀门和微型泵的方法。制造的微型阀和微型泵包括由导电纳米纤维制成的导电隔膜。通过微型阀的流体流动和微型泵的泵送作用是通过将静电力施加到导电隔膜来实现的。

36. 发明授权

US07492046B2 Electric fuses using CNTs (carbon nanotubes) 失效
标题翻译：使用碳纳米管的电熔丝
公开(公告)号：US07492046B2
公开(公告)日：2009-02-17
申请号：US11379582
申请日：2006-04-21
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： H01L23/48
CPC分类号： H01L23/53276 , H01L23/5256 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N−1 electrically conductive regions to touch the electrically conductive layer.
摘要翻译：熔丝结构及其操作方法。熔丝结构操作方法包括提供一种结构。该结构包括（a）导电层和（b）悬挂在不接触导电层的N个导电区域。 N是正整数，N大于1.N导电区域电连接在一起。结构操作方法还包括使N个导电区域的第一导电区域与导电层接触而不会使剩余的N-1导电区域接触导电层。

37. 发明授权

US07483285B2 Memory devices using carbon nanotube (CNT) technologies 有权
标题翻译：使用碳纳米管（CNT）技术的存储器件
公开(公告)号：US07483285B2
公开(公告)日：2009-01-27
申请号：US12018915
申请日：2008-01-24
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0512
摘要： Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.
摘要翻译：存储器件结构。该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测电流在第一和第三电极区域之间流动。此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位，所述感测电流不在第一和第三电极区域之间流动。

38. 发明授权

US07439081B2 Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers 有权
标题翻译：利用定向碳纳米管导电层制造集成电路芯片的方法
公开(公告)号：US07439081B2
公开(公告)日：2008-10-21
申请号：US11552771
申请日：2006-10-25
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger III , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger III , Peter H. Mitchell
IPC分类号： H01L21/00
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

39. 发明授权

US07385839B2 Memory devices using carbon nanotube (CNT) technologies 有权
标题翻译：使用碳纳米管（CNT）技术的存储器件
公开(公告)号：US07385839B2
公开(公告)日：2008-06-10
申请号：US11275010
申请日：2005-12-01
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0512
摘要： Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.
摘要翻译：结构和操作方法。该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测电流在第一和第三电极区域之间流动。此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位，所述感测电流不在第一和第三电极区域之间流动。

40. 发明授权

US07264415B2 Methods of forming alternating phase shift masks having improved phase-shift tolerance 失效
标题翻译：形成具有改进的相移公差的交替相移掩模的方法
公开(公告)号：US07264415B2
公开(公告)日：2007-09-04
申请号：US10798908
申请日：2004-03-11
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell , Larry Alan Nesbit
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F1/30
摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.
摘要翻译：用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。图案层从手柄晶片转移到掩模板。相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

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