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31. 发明专利

JP2010157283A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010157283A
公开(公告)日：2010-07-15
申请号：JP2008334431
申请日：2008-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUOKA NORIYOSHI , OSAWA TAKASHI
IPC分类号： G11C11/407 , G11C11/404
CPC分类号： G11C11/404 , G11C8/10 , G11C11/4097 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide a memory in which disturbance for a non-selection memory cell is prevented when data is written.
SOLUTION: A memory is provided corresponding to first and second word lines WLL0, WLL1 being adjacent to each other, is also provided with source lines corresponding to the first and the second word lines, when "0" purge is performed for a memory cell connected to the first word line WLL0, a driver applies voltage VWLH to WLL0 so as to form a channel in the memory cell connected to the WLL0, and voltage of a selection source line SLL01 corresponding to the WLL0 is shifted in the direction separated from voltage of the WLL0. Moreover, voltage of the second word line WLL1 is shifted in the same direction as the shift direction of the selection source line voltage, next, "1" is written selectively in memory cells connected to WLL0. Then, the driver shifts voltage of SLL01 and voltage of WLL1 in the direction of approaching to voltage of WLL0.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种当写入数据时防止非选择存储单元的干扰的存储器。解决方案：对应于彼此相邻的第一和第二字线WLL0，WLL1提供的存储器还提供有与第一和第二字线对应的源极线，当对于第一和第二字线执行“0” 存储单元连接到第一字线WLL0，驱动器向WLL0施加电压VWLH，以在连接到WLL0的存储单元中形成通道，并且与WLL0相对应的选择源极线SLL01的电压在分离的方向上偏移从WLL0的电压。此外，第二字线WLL1的电压沿与选择源极线电压的移动方向相同的方向移位，接下来，在连接到WLL0的存储单元中选择性地写入“1”。然后，驱动器将SLL01的电压和WLL1的电压接近WLL0的电压。版权所有（C）2010，JPO＆INPIT

32. 发明专利

JP2008263133A Semiconductor storage device and its driving method 审中-公开
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：JP2008263133A
公开(公告)日：2008-10-30
申请号：JP2007106069
申请日：2007-04-13
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HIGASHI TOMOKI , OSAWA TAKASHI , FUKUDA MAKOTO
IPC分类号： H01L27/10 , G11C11/401 , G11C11/405
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device into which data can be written effectively and which has a small memory cell size.
SOLUTION: The semiconductor storage device includes a semiconductor layer 30 provided on an embedded insulating film 20 on a semiconductor substrate 10; a source layer S and a drain layer D provided in the semiconductor layer; a body B provided in the semiconductor layer located between the source layer and the drain layer, which is electrically afloat and which stores electric charges to store data or discharges them; an emitter layer E which contacts with the source layer and has an opposite conductivity type to the source layer; word lines WL provided for memory cells arranged in a first direction among a plurality of two-dimensionally disposed memory cells including the source layer, drain layer, and a body; source lines SL connected with the source layers of the memory cells arranged in the first direction; and bit lines BL connected with the drain layers of the memory cells arranged in a second direction intersecting the first direction.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以有效地写入数据并且具有小的存储单元大小的半导体存储装置。解决方案：半导体存储装置包括设置在半导体衬底10上的嵌入绝缘膜20上的半导体层30; 设置在半导体层中的源极层S和漏极层D; 设置在位于源极层和漏极层之间的半导体层中的主体B，其被电浮动并且存储电荷以存储数据或将其放电; 与源极层接触并具有与源极层相反的导电类型的发射极层E; 设置在包括源极层，漏极层和主体的多个二维布置的存储单元中的沿第一方向布置的存储单元的字线WL; 源极线SL与沿第一方向布置的存储单元的源极层连接; 以及与沿与第一方向相交的第二方向布置的存储单元的漏极层连接的位线BL。版权所有（C）2009，JPO＆INPIT

33. 发明专利

JP2008117489A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008117489A
公开(公告)日：2008-05-22
申请号：JP2006301377
申请日：2006-11-07
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： G11C11/404 , G11C11/407 , G11C11/4096 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/403 , G11C8/08 , G11C11/4076 , G11C2211/4016 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which ensures a large signal difference between data "0" and "1", with high yield. SOLUTION: The device is equipped with: a memory cell MC including a source layer S, a drain layer D, and a floating body B provided between the source layer and drain layer, and storing data by the number of majority carriers in the floating body; a word line WL connected to a gate of the memory cell and extended to a first direction; a bit line BL connected to the drain layer of the memory cell and extended to a second direction different from the first direction; a source line SL connected to the source layer of the memory cell and extended to the first direction; a sense amplifier S/A connected to the bit line to detect the data stored in the selected memory cell; and drivers WLD, SLD for applying a voltage to the word line so that a channel is formed on the memory cell when binary data showing a small number of majority carriers, are written into the memory cell and for shifting the voltage of the source line to the inverse direction. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种以高产量确保数据“0”和“1”之间的大信号差的半导体存储装置。解决方案：该器件配备有：存储单元MC，其包括源极层S，漏极层D和设置在源极层和漏极层之间的浮动体B，并且通过多数载流子的数量存储数据浮体; 连接到存储器单元的栅极并延伸到第一方向的字线WL; 连接到存储单元的漏极层并延伸到与第一方向不同的第二方向的位线BL; 连接到存储单元的源层并延伸到第一方向的源极线SL; 连接到位线的读出放大器S / A，以检测存储在所选存储单元中的数据; 以及用于向字线施加电压的驱动器WLD，SLD，使得当显示少量多数载流子的二进制数据被写入存储单元并且将源极线的电压移位到存储器单元中时，在存储器单元上形成通道反方向。版权所有（C）2008，JPO＆INPIT

34. 发明专利

JP2007134012A Semiconductor memory device and driving method of semiconductor memory device 有权
标题翻译：半导体存储器件的半导体存储器件和驱动方法
公开(公告)号：JP2007134012A
公开(公告)日：2007-05-31
申请号：JP2005328593
申请日：2005-11-14
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HIGASHI TOMOKI , OSAWA TAKASHI
IPC分类号： G11C11/407 , G11C11/404 , G11C11/4091
CPC分类号： G11C8/08 , G11C7/065 , G11C7/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C2207/065 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which data can be written in a memory cell with lower power consumption as compared with the conventional one. SOLUTION: The semiconductor memory device 100 is provided with: memory cells MC including a floating body region in an electrically floating state and storing data by accumulating or discharging electric charges in the floating body region; a memory cell array MCA including a plurality of the memory cells; word lines WL connected to gates of the memory cells; bit lines BL connected to drains or sources of the memory cells; a sense amplifier S/A connected to the bit lines; and a decoder RD in which when data "1" is written in the memory cell, a first potential is applied to the word line, and when data "0" is written in the memory cell a second potential being different from the first potential is applied to the word line. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器件，其中可以将数据写入具有较低功耗的存储单元中，与常规存储器件相比。解决方案：半导体存储器件100具有：存储单元MC，其包括处于浮动状态的浮动体区域，并且通过在浮动体区域中积累或放电电荷来存储数据; 包括多个存储单元的存储单元阵列MCA; 连接到存储器单元的栅极的字线WL; 位线BL连接到存储器单元的漏极或源极; 连接到位线的读出放大器S / A; 以及解码器RD，其中当数据“1”被写入存储器单元中时，第一电位被施加到字线，并且当数据“0”被写入存储器单元中时，与第一电位不同的第二电位是应用于字线。版权所有（C）2007，JPO＆INPIT

35. 发明专利

JP2006338793A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2006338793A
公开(公告)日：2006-12-14
申请号：JP2005162828
申请日：2005-06-02
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA KATSUYUKI , HATSUDA KOSUKE , OSAWA TAKASHI
IPC分类号： G11C11/409 , G11C11/404
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor memory device which can perform a read operation at high speed and accurately without increasing a circuit scale. SOLUTION: A sense amplifier has transistors Q1, Q2 switching conduction or interruption of a pair of bit lines BLL, bBLL and a pair of sense nodes SA, bSA, transistors Q3, Q4 switching conduction/interruption of a pair of bit lines BLR, bBLR and a pair of sense nodes SA, bSA, an initial sense circuit 21, transistors Q5 to Q8 constituting a latch circuit 22 performing a latch operation after initial sense, transfer gates TG1 to TG4 controlling rewriting of data for performing controlling refresh, and a transistor Q11 short-circuiting the pair of sense nodes SA and bSA at the time of standby. Since circuit constitution of the sense node SA side and circuit constitution of the sense node bSA are symmetric, correct sense operation can be performed even when data of any logic is read. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：实现可以在不增加电路规模的情况下高速且准确地执行读取操作的半导体存储器件。解决方案：读出放大器具有晶体管Q1，Q2切换一对位线BLL，bBLL的导通或中断，以及一对感测节点SA，bSA，晶体管Q3，Q4切换一对位线的导通/中断 BLR，bBLR和一对感测节点SA，bSA，初始感测电路21，构成在初始感测之后执行锁存操作的锁存电路22的晶体管Q5至Q8，控制重写用于执行控制刷新的数据的传输门TG1至TG4，以及晶体管Q11在待机时短路一对感测节点SA和bSA。由于感测节点SA侧的电路结构和感测节点bSA的电路结构是对称的，所以即使读取任何逻辑的数据，也可以执行正确的感测操作。版权所有（C）2007，JPO＆INPIT

36. 发明专利

JP2006127665A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006127665A
公开(公告)日：2006-05-18
申请号：JP2004316043
申请日：2004-10-29
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HIGASHI TOMOKI , OSAWA TAKASHI
IPC分类号： G11C11/406 , G11C11/401 , G11C11/407 , G11C11/409
CPC分类号： G11C11/404 , G11C11/4099 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a reference memory cell that generates reference potential with less variation and does not need any refresh operation. SOLUTION: The semiconductor storage device 100 includes an information memory cell MC that writes and reads data, a memory cell array MCA in which information memory cells are disposed in matrix, information word lines WL connected to information memory cells on respective rows of the memory cell array, information bit lines BL connected to information memory cells on respective columns of the memory cell array, a reference memory cell DMC that stores a single type of digital data for generating reference potential used for identifying data in the information memory cell, a reference bit line DBL connected to the reference memory cell, and a sense amplifier SA connected to the information bit line and the reference bit lines. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有参考存储单元的半导体存储单元，该参考存储单元产生具有较小变化的参考电位，并且不需要任何刷新操作。解决方案：半导体存储装置100包括写入和读取数据的信息存储单元MC，其中以矩阵形式布置信息存储单元的存储单元阵列MCA，连接到各行上的信息存储单元的信息字线WL 存储单元阵列，连接到存储单元阵列的相应列上的信息存储单元的信息位线BL，存储用于产生用于识别信息存储单元中的数据的参考电位的单一类型的数字数据的参考存储单元DMC，连接到参考存储单元的参考位线DBL和连接到信息位线和参考位线的读出放大器SA。版权所有（C）2006，JPO＆NCIPI

37. 发明专利

JP2006073627A Semiconductor integration device 审中-公开
标题翻译：半导体集成器件
公开(公告)号：JP2006073627A
公开(公告)日：2006-03-16
申请号：JP2004252757
申请日：2004-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/108 , H01L29/786
CPC分类号： H01L29/7322 , H01L27/1203 , H01L29/735 , H01L29/8611
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit of which the device characteristic is not degraded, and wherein a bipolar transistor can be formed even if an embedded oxide film in an SOI substrate is made thin.
SOLUTION: An FBC 4, an NFET 5, and a PFET 6 are separately formed on the upper surface of an embedded oxide film 2 in an SOI substrate 3. An n well diffusion area 7 is formed in a p supporting substrate 1 beneath the FBC 4 while it is in contact with the embedded oxide film 2. A p well diffusion area 8 is formed in the p supporting substrate 1 beneath the NFET 5. An n well diffusion area 9 is formed in the p supporting substrate 1 beneath the PFET 6. The p well diffusion area 8 and the n well diffusion area 9 are formed on the lower surface side of the embedded oxide film 2 conforming to formation points of the NFET 5 and the PFET 6, and specified voltages are applied to the respective well diffusion areas. As a result, no back channel is formed in the NFET 5 and the PFET 6, thereby improving a device characteristic.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供器件特性不劣化的半导体集成电路，并且即使SOI衬底中的嵌入的氧化物膜变薄，也可以形成双极晶体管。解决方案：在SOI衬底3中的嵌入式氧化膜2的上表面上分别形成FBC 4，NFET 5和PFET 6。在p支撑衬底1中形成n阱扩散区域7 FBC4同时与嵌入的氧化物膜2接触。在P支撑衬底1上形成p阱扩散区域8，在NFET 5下面。在p支撑衬底1的下面形成n阱扩散区域9 P阱6.扩散区域8和n阱扩散区域9形成在符合NFET 5和PFET 6的形成点的嵌入氧化膜2的下表面侧上，并且将特定的电压施加到相应的扩散区。结果，在NFET 5和PFET 6中不形成背沟道，从而提高器件特性。版权所有（C）2006，JPO＆NCIPI

38. 发明专利

JP2006073061A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006073061A
公开(公告)日：2006-03-16
申请号：JP2004253059
申请日：2004-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： G11C11/407 , G11C11/404
CPC分类号： G11C11/4076 , G11C7/06 , G11C7/22 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： PROBLEM TO BE SOLVED: To normally perform data writing to a memory cell even when data can not be written in the memory cell within a column selection period of a column selection signal. SOLUTION: A semiconductor memory device is provided with a WCSL timer 10 generating a writing control signal WCSL maintaining a high level for a prescribed period even if the level of a column selection line CSL is made low. When the selection period of the column selection line CSL is shorter than the time required for data writing of an FBC21, the writing control signal WCSL is maintained in an active state (a high level) during a prescribed period after the column selection line CSL is made to be in a non-selection state. Thereby, data writing to the FBC21 can be normally performed even when time is required for data writing of the FBC21. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使在列选择信号的列选择周期内的数据不能写入存储单元中时，也能正常地对存储单元执行数据写入。解决方案：半导体存储器件设置有WCSL定时器10，即使列选择线CSL的电平为低，也产生保持高电平达规定周期的写入控制信号WCSL。当列选择线CSL的选择周期短于FBC21的数据写入所需的时间时，写入控制信号WCSL在列选择线CSL为“是”之后的规定期间内保持在活动状态（高电平）使其处于非选择状态。因此，即使在FBC21的数据写入需要时间的情况下，也能够正常地进行对FBC21的写入。版权所有（C）2006，JPO＆NCIPI

39. 发明专利

JP2006073055A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2006073055A
公开(公告)日：2006-03-16
申请号：JP2004252846
申请日：2004-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： G11C11/409
CPC分类号： G11C16/28 , G11C7/062 , G11C7/18 , G11C11/404 , G11C11/4091 , G11C11/4097 , G11C2207/005 , G11C2207/063 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a sense amplifier capable of performing more stable sense operation.
SOLUTION: The sense amplifier has current mirror circuits 25 and 27 having first and second current paths directly or indirectly connected to a pair of bit lines and current comparison circuits 3 and 5 connected to the first and the second current paths and comparing currents flowing in memory cells to be read out with a prescribed reference current. The current mirror circuit has a first transistor 27 or 25 wherein a gate and a drain are short-circuited and the reference current flows between a source and the drain and a second transistor 27 or 25 wherein a gate together with the gate of the first transistor is connected to a drain and a current passing through a FBC3 to be read out flows between a source and the drain. Even if an activated wordline is changed, more stable sense operation is made possible, since a dummy cell 5 is always connected to the current path of the transistor wherein the gate and the drain of the current mirror circuit in the sense amplifier are short-circuited.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有能够执行更稳定的感测操作的读出放大器的半导体存储器件。解决方案：读出放大器具有电流镜电路25和27，其具有直接或间接连接到一对位线的第一和第二电流路径以及连接到第一和第二电流路径的电流比较电路3和5，并且比较电流在存储单元中流动以用规定的参考电流读出。电流镜电路具有第一晶体管27或25，其中栅极和漏极短路并且参考电流在源极和漏极之间流动，以及第二晶体管27或25，其中栅极与第一晶体管的栅极连接到漏极，并且通过待读出的FBC3的电流在源极和漏极之间流动。即使激活的字线被改变，也可以进行更稳定的感测操作，因为虚设单元5总是连接到晶体管的电流路径，其中读出放大器中的电流镜像电路的栅极和漏极短路。版权所有（C）2006，JPO＆NCIPI

40. 发明专利

JP2005251791A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005251791A
公开(公告)日：2005-09-15
申请号：JP2004056298
申请日：2004-03-01
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L21/762 , G11C11/401 , H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/12 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10894 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device wherein a rate of area exclusively used by memory cells is increased by increasing the density of the memory cells while reducing an area exclusively used by a peripheral circuit and a logic circuit.
SOLUTION: The semiconductor memory device 100 comprises a semiconductor substrate 10, an insulation layer 20 formed on the semiconductor substrate, a semiconductor layer 30 formed on the insulation layer, while being insulated from the semiconductor substrate, source region 31 and drain region 33 formed in the semiconductor layer, and body region 35 formed between the source region 31 and the drain region 33. The semiconductor memory device 100 includes the memory cells MC which store data by accumulating/releasing electric charges to the body region 35, memory cell lines MCL which are constructed from a plurality of memory cells MC arranged in the channel lengthwise direction, memory cell arrays MCA which are constructed from a plurality of memory cell lines arranged in the channel widthwise direction of the memory cells, and an element isolation region which surrounds each of the plurality of memory cells MC.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储器件，其中通过增加存储器单元的密度来增加由存储单元专门使用的区域的速率，同时减少由外围电路和逻辑电路专门使用的区域。解决方案：半导体存储器件100包括半导体衬底10，形成在半导体衬底上的绝缘层20，形成在绝缘层上的半导体层30，同时与半导体衬底绝缘，源极区31和漏极区 33，形成在源极区域31和漏极区域33之间的主体区域35.半导体存储器件100包括通过将电荷累积/释放到体区35来存储数据的存储单元MC，存储单元由沿通道长度方向布置的多个存储单元MC构成的线MCL，由沿着存储单元的通道宽度方向布置的多个存储单元线构成的存储单元阵列MCA和元件隔离区，围绕多个存储单元MC中的每一个。版权所有（C）2005，JPO＆NCIPI

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