专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20090173997A1 MOSFET AND METHOD FOR MANUFACTURING MOSFET 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20090173997A1
公开(公告)日：2009-07-09
申请号：US12090451
申请日：2006-10-06
申请人： Keiko Fujihira , Naruhisa Miura , Kenichi Ohtsuka , Masayuki Imaizumi
发明人： Keiko Fujihira , Naruhisa Miura , Kenichi Ohtsuka , Masayuki Imaizumi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.
摘要翻译：本发明提供了提供高击穿电压和低导通状态损耗（高沟道迁移率和低栅极阈值电压）并且可以容易地实现正常关断的MOSFET等。根据本发明的由碳化硅制成的MOSFET的漂移层2具有第一区域2a和第二区域2b。第一区域2a是从表面到第一给定深度的区域。第二区域2b形成在比第一给定深度更深的区域中。第一区域2a的杂质浓度低于第二区域2b的杂质浓度。

32. 发明授权

US09324782B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09324782B2
公开(公告)日：2016-04-26
申请号：US14344195
申请日：2012-11-09
申请人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
发明人： Naruhisa Miura , Shiro Hino , Kenichi Ohtsuka
IPC分类号： H01L29/06 , H01L29/12 , H01L29/66 , H01L29/78 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/7811
摘要： A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the semiconductor layer, and a plurality of the unit cells is coupled in a chain manner to form a unit chain structure with a constriction. The certain shape of the unit cell is defined by an outer edge of a virtual region of the semiconductor layer defined so as to include the source region and the well region inside and by respective outer edges of the source region and the well region at a joint with a different unit cell. An active region is composed of a plurality of the unit chain structures. The unit chain structures are arranged so as to avoid generation of a gap between the unit cells of adjacent ones of the unit chain structures.
摘要翻译：半导体层，阱区和源极区形成单元。单元电池在半导体层的主表面的平面图中被限定为一定的形状，并且多个单元电池以链状的方式耦合以形成具有缩小的单位链结构。单元电池的特定形状由半导体层的虚拟区域的外边缘限定，以便包括源极区域和阱区域以及源极区域和在接合处的阱区域的相应外边缘与不同的单元格。有源区域由多个单位链结构组成。单元链结构被布置为避免在相邻单元链结构的单元电池之间产生间隙。

33. 发明授权

US08492836B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08492836B2
公开(公告)日：2013-07-23
申请号：US13500659
申请日：2009-10-14
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/66068
摘要： In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
摘要翻译：在根据本发明的半导体器件中，设置在功率半导体器件的外周部分中的p型阱区被分成两部分，即内部和外部，并且具有更大的场氧化物膜膜厚比栅极绝缘膜设置在外部的阱区域到阱区的内周的内侧。因此，可以防止在栅极绝缘膜中由于切换中的位移电流的流动而产生的电压引起的电介质击穿。

34. 发明申请

US20130140582A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130140582A1
公开(公告)日：2013-06-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12 , H01L21/265
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11′) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple. The fourth RESURF layer (14) is configured with small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) and small regions (15′) having an implantation amount equal to that of the fifth RESURF layer (15) being alternately arranged in multiple.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。在活性区域（2）附近形成包括具有相对低浓度的P型杂质的多个P型注入层的RESURF层（101）。 RESURF层（101）包括第一RESURF层（11），第二RESURF层（12），第三RESURF层（13），第四RESURF层（14）和第五RESURF层（15）从P型基底（2）侧顺序地包围P型基底（2）。第二RESURF层（12）配置有具有等于第一RESURF层（11）的注入量的小区域（11'）和具有等于第三RESURF层的注入量的小区域（13'）（13）交替布置成多个。第四RESURF层（14）配置有具有等于第三RESURF层（13）的注入量的小区域（13'）和具有等于第五RESURF层的注入量的小区域（15'）（15）交替排列成多个。

35. 发明授权

US08513735B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08513735B2
公开(公告)日：2013-08-20
申请号：US13127564
申请日：2009-06-30
申请人： Shuhei Nakata , Shoyu Watanabe , Kenichi Otsuka , Naruhisa Miura
发明人： Shuhei Nakata , Shoyu Watanabe , Kenichi Otsuka , Naruhisa Miura
IPC分类号： H01L29/78
CPC分类号： H01L29/66068 , H01L29/41758 , H01L29/7827
摘要： A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow.
摘要翻译：具有大面积的P阱区和栅电极的功率半导体器件的结构通过具有比栅绝缘膜的厚度大的场氧化膜彼此相对，使得P阱具有大面积的栅极绝缘膜和栅电极不通过栅极绝缘膜彼此相对，或者栅电极不设置在包括具有大面积的P阱区的栅极绝缘膜的上方。

36. 发明申请

US20130020586A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130020586A1
公开(公告)日：2013-01-24
申请号：US13638970
申请日：2011-04-07
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/0878 , H01L29/1095 , H01L29/1602 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/66712 , H01L29/781 , H01L29/7811
摘要： A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.
摘要翻译：具有低反馈电容和低开关损耗的半导体器件。半导体器件包括：衬底; 形成在所述半导体衬底的表面上的漂移层; 多个第一阱区，形成在所述漂移层的表面上; 源区域，其是形成在每个第一阱区域的表面上的区域，并且限定插入在该区域和漂移层之间的每个第一阱区域的沟道区域; 形成在所述沟道区域上的栅电极和穿过栅极绝缘膜的所述漂移层; 以及埋在栅电极下方的漂移层内的第二阱区，并形成为分别连接到彼此相邻的每个第一阱区。

37. 发明申请

US20120061688A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件及其制造功率半导体器件的方法
公开(公告)号：US20120061688A1
公开(公告)日：2012-03-15
申请号：US13319742
申请日：2009-07-15
申请人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
发明人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film. A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of the semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of the drift layer; a second well region of the second conductivity type formed in a part of the surface layer of the drift layer at a distance from the first well region, the second well region having a smaller area than that of the first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of the first well region, the low-resistance region having a higher impurity concentration than that of the first well region; a gate insulating film formed on and in contact with a surface of the first well region; and a gate electrode formed on and in contact with a surface of the gate insulating film.
摘要翻译：在高速切换的功率半导体器件中，位移电流在切换时流动，从而产生可能导致诸如栅极绝缘膜的薄绝缘膜破坏的高电压。半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的所述第一导电类型的漂移层; 形成在漂移层的表面层的一部分中的第二导电类型的第一阱区; 第二导电类型的第二阱区形成在距第一阱区一定距离的漂移层的表面层的一部分中，第二阱区的面积比第一阱区的面积小，当在上部表面形成在所述第一阱区的表面层中的所述第一导电类型的低电阻区域，所述低电阻区域的杂质浓度高于所述第一阱区域的杂质浓度; 形成在第一阱区的表面上并与其接触的栅极绝缘膜; 以及形成在栅极绝缘膜的表面上并与栅极绝缘膜的表面接触的栅电极。

38. 发明授权

US06635938B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06635938B1
公开(公告)日：2003-10-21
申请号：US09716219
申请日：2000-11-21
申请人： Takumi Nakahata , Shigemitsu Maruno , Taisuke Furukawa , Naruhisa Miura , Toshiyuki Oishi , Yasunori Tokuda
发明人： Takumi Nakahata , Shigemitsu Maruno , Taisuke Furukawa , Naruhisa Miura , Toshiyuki Oishi , Yasunori Tokuda
IPC分类号： H01L2994
CPC分类号： H01L29/4983 , H01L21/823418 , H01L21/823468 , H01L29/41783 , H01L29/6656 , H01L29/66575 , H01L29/66628
摘要： A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.
摘要翻译：形成多晶硅氮化物膜以覆盖多晶硅栅极。通过在氧气氛中对氮化硅膜进行热处理，形成硅氧氮化物膜。通过各向异性蚀刻氧氮化硅膜和氮化硅膜，形成侧壁绝缘膜。通过外延生长，在源极和漏极区域上形成规定膜厚度的选择性硅膜。在此期间，硅岛不会沉积在侧壁绝缘膜的表面上。因此，可以获得包括具有优异的电绝缘的晶体管的半导体器件。

39. 发明授权

US08716717B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08716717B2
公开(公告)日：2014-05-06
申请号：US13816511
申请日：2011-04-15
申请人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
发明人： Tsuyoshi Kawakami , Akihiko Furukawa , Naruhisa Miura , Yasuhiro Kagawa , Kenji Hamada , Yoshiyuki Nakaki
IPC分类号： H01L29/12
CPC分类号： H01L29/12 , H01L21/0465 , H01L21/265 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/66128 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/8611 , H01L29/872
摘要： A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.
摘要翻译：在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层，第二RESURF层，第三RESURF层，第四RESURF层和第五RESURF层。第二RESURF层配置有具有等于第一RESURF层的注入量的小区域，并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。第四RESURF层配置有具有等于第三RESURF层的注入量的小区域，并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。

40. 发明授权

US08367536B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08367536B2
公开(公告)日：2013-02-05
申请号：US13319739
申请日：2010-07-16
申请人： Hiroshi Watanabe , Naruhisa Miura
发明人： Hiroshi Watanabe , Naruhisa Miura
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1608 , H01L29/66068
摘要： The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a base region deeper than the source region in the upper layer part of the drift layer.
摘要翻译：本发明包括以下步骤：（a）通过光刻法分别在漂移层上形成第一离子注入掩模和第二离子注入掩模，以形成第三离子注入掩模，第一离子注入掩模具有对应于沟道区，具有对应于源极区的第一开口，所述第二离子注入掩模定位成与所述第一离子注入掩模的外边缘接触并且被配置为形成基区; （b）使用第三离子注入掩模，用离子束从第一开口注入第一导电类型的杂质，以在碳化硅漂移层的上层部分中形成源极区; （c）在形成源极区域之后去除第一离子注入掩模; 以及（d）在除去第一离子注入掩模之后，从形成在第二离子注入掩模中的第二开口用离子束注入第二导电类型的杂质以形成比上层部分中的源极区更深的基极区的漂移层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式