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31. 发明授权

US6114192A Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame 失效
标题翻译：使用支撑框架制造具有球栅阵列封装结构的半导体器件的方法
公开(公告)号：US6114192A
公开(公告)日：2000-09-05
申请号：US114997
申请日：1998-07-14
申请人： Shigeharu Tsunoda , Junichi Saeki , Isamu Yoshida , Kazuya Ooji , Michiharu Honda , Makoto Kitano , Nae Yoneda , Shuji Eguchi , Kunihiko Nishi , Ichiro Anjoh , Kenichi Otsuka
发明人： Shigeharu Tsunoda , Junichi Saeki , Isamu Yoshida , Kazuya Ooji , Michiharu Honda , Makoto Kitano , Nae Yoneda , Shuji Eguchi , Kunihiko Nishi , Ichiro Anjoh , Kenichi Otsuka
IPC分类号： H01L21/50 , H01L21/56 , H01L21/58 , H01L21/60 , H01L23/04 , H01L23/31 , H01L21/44 , H01L21/48
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/3128 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.
摘要翻译：一种半导体塑料封装，更具体地，优选的封装结构和用于制造BGA封装的方法。树脂密封BGA封装，其中固定支撑半导体部件的支撑框架; 即IC芯片，电路板或电路膜用树脂密封，使用由上半模和下半模构成的模具，下半模具有多个突起，一个在对应于每个外部端子的位置。模具具有在其分割元件之间具有通风口的分隔结构。

32. 发明授权

US6100580A Semiconductor device having all outer leads extending from one side of a resin member 失效
标题翻译：具有从树脂构件的一侧延伸的所有外部引线的半导体装置
公开(公告)号：US6100580A
公开(公告)日：2000-08-08
申请号：US167736
申请日：1998-10-07
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

33. 发明授权

US5981315A Semiconductor device 失效
公开(公告)号：US5981315A
公开(公告)日：1999-11-09
申请号：US166532
申请日：1998-10-06
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
IPC分类号： H01L21/52 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34 , H01L21/44
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

34. 发明授权

US5821606A Semiconductor device 失效
公开(公告)号：US5821606A
公开(公告)日：1998-10-13
申请号：US790985
申请日：1997-01-29
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

35. 发明授权

US5530286A Semiconductor device 失效
公开(公告)号：US5530286A
公开(公告)日：1996-06-25
申请号：US293555
申请日：1994-08-22
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34 , H01L23/48 , H01L23/52
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

36. 发明授权

US4989166A Method for synthesizing analysis model and flow analysis system 失效
标题翻译：综合分析模型和流量分析系统的方法
公开(公告)号：US4989166A
公开(公告)日：1991-01-29
申请号：US340480
申请日：1989-04-19
申请人： Shingo Akasaka , Kazuhiro Sugino , Junichi Saeki , Kunihiko Nishi , Hisashi Onari
发明人： Shingo Akasaka , Kazuhiro Sugino , Junichi Saeki , Kunihiko Nishi , Hisashi Onari
IPC分类号： B29C33/38 , B29C45/76 , G06F17/50 , G06T17/00
CPC分类号： G06T17/00 , B29C33/3835 , B29C45/76 , G06F17/5018 , G06F2217/16 , G06F2217/41
摘要： The present invention is applied to the design of a mold for a semiconductor or the like and provides a method for synthesizing analysis models, in which analysis programs corresponding to shapes and features of an object to be analyzed are registered in advance in a numerical analysis system, the analysis programs are made to correspond to partial shapes divided according to the shapes and features of the object to be analyzed and are partially modelled, whereas input and output items between adjacent portions are controlled on the basis of the positional relationship between the portions and input and output information of the analysis programs placed in correspondence to the portions. The invention further provides a flow analysis system for computing a flow state of material to evaluate a shape of a flowpassage, a flow control condition, material and the like, the system comprising input means for inputting a flowpassage shape of a mold, properties of material and flow control conditions, model synthesizing means for extracting a feature of the flowpassage shape, judging an adaptability with the already registered analysis model from the extracted features and synthesizing flow analysis models capable of analyzing the entire flowpassage, and program execution means for removing programs corresponding to the synthesized model to sequentially execute them.

37. 发明授权

US4954301A Transfer molding process and an apparatus for the same 失效
标题翻译：传递成型工艺及其设备
公开(公告)号：US4954301A
公开(公告)日：1990-09-04
申请号：US378505
申请日：1989-07-12
申请人： Junichi Saeki , Aizo Kaneda , Kunihiko Nishi
发明人： Junichi Saeki , Aizo Kaneda , Kunihiko Nishi
IPC分类号： B29C45/02 , B29C45/76 , B29L31/34 , H01L21/00
CPC分类号： H01L21/67126 , B29C45/76 , B29C45/02
摘要： A transfer molding process and an apparatus for carrying out the same for sealing electronic devices, such as semiconductor devices, in a resin by driving a plunger downward in a pot to inject the resin into a mold. In injecting a resin into a mold by driving the plunger downward, the rotary motion of the output shaft of an electric motor is converted into a linear motion to drive the plunger downward, the downward displacement of the plunger from the initial position is detected, and pressure applied to the plunger is varied according to the displacement of the plunger. Thus, the transfer molding process and the apparatus for carrying out the same reduces defects, such as voids and incompletely filled parts, in the resin-sealed device, and prevents burrs and the deformation of the insert during the transfer molding operation.

38. 发明授权

US08095348B2 Support system, support method and support program of resin molded article 有权
标题翻译：树脂模制品的设计支持系统，支持方法和支持程序
公开(公告)号：US08095348B2
公开(公告)日：2012-01-10
申请号：US12038966
申请日：2008-02-28
申请人： Junichi Saeki , Tsutomu Kono
发明人： Junichi Saeki , Tsutomu Kono
IPC分类号： G06G7/50 , G06G7/58 , G06G7/48 , G06F7/60 , G06F19/00 , B29C39/00 , B29C45/17 , G01N3/60
CPC分类号： G06F17/5009 , G06F2217/16 , G06F2217/41 , G06F2217/80
摘要： A model creation portion having a obstacle in a space includes two creation portions, one is to separate them and another is to combine them which handles, as porous media, an obstacle in which narrow spaces are regularly arranged. A thermosets flow analysis portion includes two analysis portions to separate and combine them, each of them has a viscosity equation for thermosets. The space/obstacle separation analysis portion analyzes by combining the viscosity equation with conservation equations of mass, momentum and energy, and the space/obstacle combination analysis portion analyzes by combining the viscosity equation with a conservation equation directed to a shape simplified as porous media. Resin flow behavior is analyzed while data in an interface between two models is delivered to each other, to accurately predict filling behavior at the time of injecting resin of thermosets molded articles having the complex obstacles.
摘要翻译：在空间中具有障碍物的模型创建部分包括两个创建部分，一个是分离它们，另一个是组合它们，作为多孔介质，其中狭窄空间被规则排列的障碍物。热固性流动分析部分包括分离和组合它们的两个分析部分，每个分析部分具有热固性材料的粘度方程式。空间/障碍物分离分析部分通过将粘度方程与质量，动量和能量的守恒方程组合，以及通过将粘度方程与针对简化为多孔介质的形状的守恒方程相结合来分析空间/障碍物组合分析部分。分析树脂流动行为，同时将两个模型之间的界面中的数据彼此交付，以准确地预测在注入具有复杂障碍物的热固性成型制品的树脂时的填充行为。

39. 发明申请

US20080234989A1 DESIGN SUPPORT SYSTEM, SUPPORT METHOD AND SUPPORT PROGRAM OF RESIN MOLDED ARTICLE 有权
标题翻译：树脂模型设计支持系统，支持方法和支持方案
公开(公告)号：US20080234989A1
公开(公告)日：2008-09-25
申请号：US12038966
申请日：2008-02-28
申请人： Junichi Saeki , Tsutomu Kono
发明人： Junichi Saeki , Tsutomu Kono
IPC分类号： G06G7/57 , G06F17/50 , G06G7/56
CPC分类号： G06F17/5009 , G06F2217/16 , G06F2217/41 , G06F2217/80
摘要： To quick and accurately predict filling behavior at the time of injecting resin of thermosets molded articles having a complex obstacle. A model creation portion includes a space/obstacle separation model creation portion and a space/obstacle combination model creation portion. The space/obstacle combination model creation portion handles, as porous media, an obstacle in which narrow spaces are regularly arranged. A thermosets flow analysis portion includes a space/obstacle separation analysis portion and a space/obstacle combination analysis portion, and each of them has a viscosity equation for thermosets. The space/obstacle separation analysis portion analyzes by combining the viscosity equation with conservation equations of mass, momentum and energy, and the space/obstacle combination analysis portion analyzes by combining the viscosity equation with a conservation equation directed to a shape simplified as porous media. Resin flow behavior is analyzed while data in an interface between a space/obstacle separation model and a space/obstacle combination model is delivered to each other.
摘要翻译：为了快速，准确地预测在注入具有复杂障碍物的热固性成型制品的树脂时的填充行为。模型创建部分包括空间/障碍物分离模型创建部分和空间/障碍物组合模型创建部分。空间/障碍物组合模型创建部分作为多孔介质处理狭窄空间被规则排列的障碍物。热固性流动分析部分包括空间/障碍物分离分析部分和空间/障碍物组合分析部分，并且它们中的每一个具有热固性材料的粘度方程式。空间/障碍物分离分析部分通过将粘度方程与质量，动量和能量的守恒方程组合，以及通过将粘度方程与针对简化为多孔介质的形状的守恒方程相结合来分析空间/障碍物组合分析部分。当空间/障碍物分离模型和空间/障碍物组合模型之间的界面中的数据彼此传递时，分析树脂流动行为。

40. 发明申请

US20060004481A1 Three-dimensional foam analysis method, product design aiding method using the analysis method, and recording medium recording these methods 有权
标题翻译：三维泡沫分析方法，使用分析方法的产品设计辅助方法，以及记录这些方法的记录介质
公开(公告)号：US20060004481A1
公开(公告)日：2006-01-05
申请号：US11153468
申请日：2005-06-16
申请人： Tsutomu Kono , Junichi Saeki
发明人： Tsutomu Kono , Junichi Saeki
IPC分类号： B29C45/00
CPC分类号： B29C44/60 , B29K2075/00 , B29K2105/04 , G06F17/5018 , G06F2217/16 , G06F2217/41
摘要： To regulate the passage structure of a foaming die and the injected amount of foaming material, the flow behavior of the foaming material is analyzed by obtaining a flow velocity and a pressure by inputting the density as a function, including the elapsed time from the passage through an injection port to the foaming die and the thickness, and substituting a calculated density in equations of continuity and motion. In the analysis, the viscosity of the foaming material is used as a function including a time term. The boundary and molding conditions are corrected when the calculation does not converge. The density and pressure distributions of the foaming material are determined when the calculation converges. When the density and pressure distributions depart from design tolerances, the foaming passage structure and foaming material injected amount are regulated by an analysis program that corrects the model form, physical property or molding condition.
摘要翻译：为了调节发泡模具的通道结构和发泡材料的注入量，通过输入密度作为函数，通过获得流速和压力来分析发泡材料的流动行为，包括从通过到经过的时间喷射口到发泡模具和厚度，并以连续性和运动方程代替计算的密度。在分析中，起泡材料的粘度用作包括时间段的功能。当计算不收敛时，修正边界和成型条件。当计算收敛时，确定发泡材料的密度和压力分布。当密度和压力分布偏离设计公差时，发泡通道结构和发泡材料注入量通过校正模型形状，物理性能或成型条件的分析程序来调节。

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