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31. 发明授权

US08828831B2 Epitaxial replacement of a raised source/drain 有权
标题翻译：升起的源极/漏极的外延替代
公开(公告)号：US08828831B2
公开(公告)日：2014-09-09
申请号：US13355691
申请日：2012-01-23
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/772 , H01L29/417 , H01L21/8238
CPC分类号： H01L29/0603 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/092 , H01L29/165 , H01L29/41725 , H01L29/66628 , H01L29/772 , H01L29/78
摘要： Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.
摘要翻译：公开了一种半导体制品，其包括半导体衬底; 栅极结构具有与栅极结构的导电材料相邻的间隔物，其中间隔物的角被刻面以在刻面间隔物和半导体衬底之间产生刻面空间; 以及与栅极结构相邻的升高的源极/漏极，所述升高的源极/漏极填充所述刻面空间并具有平行于所述半导体衬底的表面。还公开了制造半导体制品的方法。

32. 发明授权

US08674447B2 Transistor with improved sigma-shaped embedded stressor and method of formation 失效
标题翻译：具有改进的σ形嵌入式应力源的晶体管及其形成方法
公开(公告)号：US08674447B2
公开(公告)日：2014-03-18
申请号：US13457980
申请日：2012-04-27
申请人： Thomas N Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/78
CPC分类号： H01L21/02609 , H01L21/265 , H01L21/28026 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L21/3086 , H01L29/165 , H01L29/66431 , H01L29/6653 , H01L29/66575 , H01L29/66636 , H01L29/7848
摘要： A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
摘要翻译：具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。各向异性蚀刻在凹槽的通道侧壁中产生刻面。小面相遇时，形成顶点。顶点的深度由第二蚀刻深度（阶梯深度）决定。顶点的横向位置由第一间隔件的厚度决定。在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。

33. 发明申请

US20140015014A1 FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES 有权
标题翻译：具有变化阈值电压的场效应晶体管
公开(公告)号：US20140015014A1
公开(公告)日：2014-01-16
申请号：US13545224
申请日：2012-07-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78
CPC分类号： H01L27/088 , H01L21/02529 , H01L21/02532 , H01L21/0257 , H01L21/02576 , H01L21/02579 , H01L21/28008 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L29/167 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/7834 , H01L29/7848
摘要： A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
摘要翻译：一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。

34. 发明申请

US20140001554A1 SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE 有权
标题翻译：封闭边缘提供外延源/排水沟的半导体器件
公开(公告)号：US20140001554A1
公开(公告)日：2014-01-02
申请号：US13534407
申请日：2012-06-27
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , G06F17/50 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L23/485 , H01L27/1203 , H01L29/0653
摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.
摘要翻译：形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域涉及对应于第二晶体管的第一晶体管和第二升高区域。第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

35. 发明申请

US20130193492A1 SILICON CARBON FILM STRUCTURE AND METHOD 审中-公开
标题翻译：硅碳膜结构与方法
公开(公告)号：US20130193492A1
公开(公告)日：2013-08-01
申请号：US13360823
申请日：2012-01-30
申请人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02447 , H01L21/02507 , H01L21/02529 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7848
摘要： An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.
摘要翻译：公开了一种改进的硅碳膜结构。膜结构包括多层硅碳和硅。多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

36. 发明授权

US09093260B2 Thin hetereostructure channel device 有权
标题翻译：薄型立体声通道装置
公开(公告)号：US09093260B2
公开(公告)日：2015-07-28
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/66 , H01L21/02 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

37. 发明授权

US09087687B2 Thin heterostructure channel device 有权
标题翻译：薄异质结构通道器件
公开(公告)号：US09087687B2
公开(公告)日：2015-07-21
申请号：US13336251
申请日：2011-12-23
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

38. 发明授权

US09059323B2 Method of forming fin-field effect transistor (finFET) structure 有权
标题翻译：形成鳍场效应晶体管（finFET）结构的方法
公开(公告)号：US09059323B2
公开(公告)日：2015-06-16
申请号：US13565838
申请日：2012-08-03
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L21/845 , H01L27/1211
摘要： Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins.
摘要翻译：各种实施例包括形成半导体结构的方法。在一个实施例中，一种方法包括：提供包括衬底和覆盖衬底的一组鳍片的前体结构; 在翅片组中的翅片之间形成虚拟外延; 掩蔽该组散热片中的第一组散热片和在一组翅片中的第一组翅片之间的虚设外延; 去除所述虚拟外延以暴露第二组散热片; 在暴露的翅片之间形成第一原位掺杂外延; 掩蔽该组散热片中的第二组翅片和在该组翅片中的第二组翅片之间的原位掺杂的外延; 揭开第一组翅片; 去除第一组翅片之间的虚拟外延层以暴露第一组翅片; 以及在所述暴露的鳍之间形成第二原位掺杂的外延。

39. 发明授权

US08866227B2 Thin semiconductor-on-insulator MOSFET with co-integrated silicon, silicon germanium and silicon doped with carbon channels 有权
标题翻译：具有共同集成硅，硅锗和掺杂碳通道的硅的薄绝缘体MOSFET
公开(公告)号：US08866227B2
公开(公告)日：2014-10-21
申请号：US13607743
申请日：2012-09-09
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/84 , H01L21/77 , H01L27/092 , H01L21/02 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域以及掺杂有碳层的硅的第三器件区域。然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

40. 发明授权

US08816436B2 Method and structure for forming fin resistors 有权
标题翻译：形成鳍式电阻的方法和结构
公开(公告)号：US08816436B2
公开(公告)日：2014-08-26
申请号：US13472605
申请日：2012-05-16
申请人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/12 , H01L23/62 , H01L29/00 , H01L27/06 , H01L21/02
CPC分类号： H01L21/845 , H01L27/0802 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.
摘要翻译：公开了一种鳍式电阻器和制造方法。散热片电阻器包括以具有外延区域的交替图案的线性图案布置的多个散热片。退火将掺杂剂从外延区域扩散到鳍片中。触头连接到端点外延区域，以允许电阻器连接到更复杂的集成电路。

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