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    • 31. 发明授权
    • Matrix-structured neural network with learning circuitry
    • 具有学习电路的矩阵结构神经网络
    • US5083285A
    • 1992-01-21
    • US419768
    • 1989-10-11
    • Takeshi ShimaYukio Kamatani
    • Takeshi ShimaYukio Kamatani
    • G06N3/063
    • G06N3/063
    • A multi-layer perceptron circuit device using integrated configuration which is capable of incorporating self-learning function and which is easily extendable. The device includes: at least one synapse blocks containing: a plurality of synapses for performing weight calculation on input signals to obtain output signals, which are arranged in planar array defined by a first and a second directions; input signal lines for transmitting the input signals to the synapses, arranged along the first direction; and output signal lines for transmitting the output signal from the synapses, arranged along the second direction not identical to the first direction; at least one input neuron blocks containing a plurality of neurons to be connected with the input signal lines; and at least one output neuron blocks containing a plurality of neurons to be connected with the output signal lines.
    • 一种使用集成配置的多层感知电路装置,其能够结合自学习功能并且易于扩展。 该装置包括:至少一个突触块,其包含:多个突触,用于对输入信号进行加权计算,以获得以由第一和第二方向限定的平面阵列排列的输出信号; 用于将输入信号传输到沿着第一方向布置的突触的输入信号线; 以及输出用于发送来自突触的输出信号的信号线,沿着与第一方向不相同的第二方向排列; 至少一个输入神经元块,其包含要与输入信号线连接的多个神经元; 以及包含要与输出信号线连接的多个神经元的至少一个输出神经元块。
    • 34. 发明授权
    • Control circuit for floating gate four-quadrant analog multiplier
    • 浮栅四象限模拟乘法器控制电路
    • US5021693A
    • 1991-06-04
    • US500309
    • 1990-03-28
    • Takeshi Shima
    • Takeshi Shima
    • G11C17/00G06G7/163G06G7/60G06N3/063G11C16/02H01L21/822H01L21/8247H01L27/04H01L29/788H01L29/792H03F3/45H03G3/10H03K19/00
    • H03F3/45076G06N3/0635
    • Disclosed is an electronic circuit comprising commonly connecting the gate end of a first transistor having a floating gate and the source end and the drain end of a second transistor having a floating gate to a first control input terminal, and commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal. The electronic circuit can repeatedly set and maintain accumulation charge amounts of the respective floating gates of the first and the second transistor at predetermined values. Also disclosed is an electronic circuit including the above electronic circuit, and further comprising commonly connecting the respective souce ends of a third and a fourth transistor to a first terminal to compose a first differential couple, providing a current source between the first terminal and a power source end or and earthed end, connecting the floating gates of the first and the third transistor together, connecting the floating gates of the second and the fourth transistor together, connecting the normal gate end of the third transistor to a first positive input terminal, and connecting the normal gate end of the fourth transistor to a first negative input terminal. The so-composed electronic circuit can repeatedly set and maintain threshold values in differential amplification at respective predetermined values. Further disclosed is an analog multiplication circuit comprising combination of these electronic circuits and an amplification circuit, which can repeatedly set and maintain weight concerning multiplication factors at predetermined values.
    • 37. 发明申请
    • IMAGE PROCESSING APPARATUS
    • 图像处理设备
    • US20140028873A1
    • 2014-01-30
    • US14110679
    • 2012-04-04
    • Mirai HiguchiMasahiro KiyoharaTakeshi ShimaTatsuhiko Monji
    • Mirai HiguchiMasahiro KiyoharaTakeshi ShimaTatsuhiko Monji
    • H04N5/235
    • H04N5/2352G06K9/2054G08B13/19647H04N5/232H04N5/23229H04N5/2353
    • There is provided an image processing apparatus that can implement image recognition processing on all of objects to be recognized, and can reduce a load of capturing and transferring images. The image processing apparatus includes: an image capturing unit that captures image information picked up by an imaging element; a processing region setting unit that sets a plurality of processing regions for the image information; a processing sequence/frequency determination unit that determines at least any one of a sequence, a frequency, and a timing of capturing the respective image information in a plurality of set processing regions, and at least any one of a sequence, a frequency, and a timing of processing the respective image information; and an image processing unit that captures the image information for each of the processing regions according to the sequence, the frequency, or the timing which has been determined, and processes the captured image information according to the sequence, the frequency, or the timing which has been determined.
    • 提供了一种能够对要被识别的所有对象执行图像识别处理的图像处理装置,并且可以减少捕获和传送图像的负担。 该图像处理设备包括:图像捕获单元,其捕获由成像元件拾取的图像信息; 处理区域设定单元,对所述图像信息设定多个处理区域; 处理序列/频率确定单元,其确定在多个集合处理区域中捕获各个图像信息的序列,频率和定时中的至少一个,以及序列,频率和 处理各图像信息的定时; 以及图像处理单元,其根据已经确定的顺序,频率或定时捕获每个处理区域的图像信息,并且根据序列,频率或时间来处理所捕获的图像信息 已经确定
    • 40. 发明申请
    • STEREO IMAGE PROCESSING DEVICE AND METHOD
    • 立体图像处理装置和方法
    • US20100328427A1
    • 2010-12-30
    • US12711787
    • 2010-02-24
    • Morihiko SAKANOMirai HiguchiTakuya NakaTakeshi ShimaShoji Muramatsu
    • Morihiko SAKANOMirai HiguchiTakuya NakaTakeshi ShimaShoji Muramatsu
    • H04N13/02H04N13/00
    • G06T7/593G06T2207/10012
    • In stereo matching based on standard area matching, in order to suppress a decrease in matching accuracy, it is effective to adaptively change a matching area in accordance with the local properties of an image. However, this requires high calculation costs. Thus, the present invention provides a stereo image processing apparatus including an image pickup unit 101 configured to take a plurality of image data using a plurality of cameras, an image memory 102 configured to store the plurality of image data taken by the image pickup unit 101, a calculated disparity storage unit 105 configured to store disparity data determined based on the plurality of image data, a matching area control unit 103 configured to set a matching area for each pixel based on the plurality of data read from the image memory 102 and the disparity data read from the calculated disparity storage unit 105, and a disparity calculating unit 104 configured to perform matching on the image data based on the plurality of image data read from the image memory 102 and the matching area for each pixel set by the matching area control unit 103 to calculate disparity data.
    • 在基于标准区域匹配的立体匹配中,为了抑制匹配精度的降低,根据图像的局部特性自适应地改变匹配区域是有效的。 然而,这需要很高的计算成本。 因此,本发明提供了一种立体图像处理装置,其包括被配置为使用多个摄像机拍摄多个图像数据的图像拾取单元101,被配置为存储由图像拾取单元101拍摄的多个图像数据的图像存储器102 被配置为存储基于多个图像数据确定的视差数据的计算出的视差存储单元105,匹配区域控制单元103,被配置为基于从图像存储器102读取的多个数据和每个像素设置匹配区域, 从计算出的视差存储单元105读取的视差数据和视差计算单元104,被配置为基于从图像存储器102读取的多个图像数据和由匹配区域设置的每个像素的匹配区域对图像数据进行匹配 控制单元103来计算视差数据。