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31. 发明授权

US06620665B1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06620665B1
公开(公告)日：2003-09-16
申请号：US09787108
申请日：2001-03-14
申请人： Gaku Sugahara , Tohru Saitoh , Minoru Kubo , Teruhito Ohnishi
发明人： Gaku Sugahara , Tohru Saitoh , Minoru Kubo , Teruhito Ohnishi
IPC分类号： H01L21338
CPC分类号： H01L29/66916 , H01L21/02164 , H01L21/02271 , H01L21/02381 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3145 , H01L21/31612 , H01L21/3185 , H01L21/823807 , H01L29/66242
摘要： A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C. or more may also be performed on a separate fabrication line. Otherwise, it suffices to only perform the high-temperature treatment at 700° C. or more on a separate line.
摘要翻译：执行用于制造包括含Ge半导体膜和用于器件的晶片的器件的晶片的工艺控制，例如在公共制造线上不包含含Ge半导体膜。在含有Ge的半导体膜的晶片在Ge基半导体膜的状态基本上露出的状态下，在700℃以上进行高温处理时，含有Ge的半导体膜被覆盖在高温处理之前由Si等制成的盖层。盖层可以形成在公共制造线上。然而，如果盖层本身的形成涉及700℃以上的高温，则在与公共制造线分开的制造线上进行。或者，盖层可以形成在与公共制造线分开的制造线上，并且在700℃以上的高温处理也可以在单独的制造线上进行。否则，仅在单独的线路上进行700℃以上的高温处理即可。

32. 发明授权

US5327012A Semiconductor device having a double-layer interconnection structure 失效
标题翻译：具有双层互连结构的半导体器件
公开(公告)号：US5327012A
公开(公告)日：1994-07-05
申请号：US993885
申请日：1992-12-23
申请人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
发明人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
IPC分类号： H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5329 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor device having a double-layer interconnection with contact portions between first and second metal films, each having a multi-layered structure, covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films, respectively, have a multi-layered structure including a sub-layer made of Al or Al alloys.
摘要翻译：提供一种具有与第一和第二金属膜之间的接触部分的双层互连的半导体器件，每个具有多层结构的接触部分被至少覆盖有氮化硅膜，其中提高了接触部分的电迁移特性。通过将通过在接触部分形成的氮化物膜的应力乘以氮化硅膜的厚度而获得的值不超过通过将氮化硅膜的厚度乘以所获得的值的2/5来获得的改进通过在非接触部分形成的氮化物膜的应力。由此，施加在第二金属膜上的应力减小，从而将接触部分的电迁移寿命提高大约一个数量级。第一和第二金属膜分别具有包括由Al或Al合金制成的子层的多层结构。

33. 发明授权

US5198884A Semiconductor devices having a double-layer interconnection structure 失效
标题翻译：具有双层互连结构的半导体器件
公开(公告)号：US5198884A
公开(公告)日：1993-03-30
申请号：US675833
申请日：1991-03-27
申请人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
发明人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
IPC分类号： H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： A semiconductor device having a double-layer interconnection with contact portions between first and second metal films covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films are made of Al or Al-based alloys.
摘要翻译：提供了具有与至少覆盖有氮化硅膜的第一和第二金属膜之间的接触部分的双层互连的半导体器件，其中改善了接触部分处的电迁移特性。通过将通过在接触部分形成的氮化物膜的应力乘以氮化硅膜的厚度而获得的值不超过通过将氮化硅膜的厚度乘以所获得的值的2/5来获得的改进通过在非接触部分形成的氮化物膜的应力。由此，施加在第二金属膜上的应力减小，从而将接触部分的电迁移寿命提高大约一个数量级。第一和第二金属膜由Al或Al基合金制成。

34. 发明授权

US07049681B2 Bipolar transistor device having phosphorous 失效
标题翻译：具有磷的双极晶体管器件
公开(公告)号：US07049681B2
公开(公告)日：2006-05-23
申请号：US10972442
申请日：2004-10-26
申请人： Teruhito Ohnishi , Akira Asai
发明人： Teruhito Ohnishi , Akira Asai
IPC分类号： H01L29/02
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.
摘要翻译：作为由i-Si 1-x Ge x x构成的基底的Si 1-x Ge 2 x层111b， / SUB层，并且在集电极层102上形成有Si + 1-xSi Ge层，并且Si覆盖层111a 因为发射极形成在p + 1 Si 1-x Ge层上。发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的N +和/或多个多晶硅层129b组成，在基底开口118中的Si覆盖层111a上形成含有高浓度的磷的多晶硅层129a。通过抑制Si覆盖层111a的基底层中的杂质浓度分布适当地保持以过高浓度的磷（P）掺杂。 Si覆盖层111a的上部可以含有p型杂质。因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

35. 发明申请

US20050082571A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050082571A1
公开(公告)日：2005-04-21
申请号：US10972442
申请日：2004-10-26
申请人： Teruhito Ohnishi , Akira Asai
发明人： Teruhito Ohnishi , Akira Asai
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/165 , H01L29/732 , H01L29/737 , H01L29/739
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.
摘要翻译：作为由i-Si 1-x Ge x x构成的基底的Si 1-x Ge 2 x层111b， / SUB层，并且在集电极层102上形成有Si + 1-xSi Ge层，并且Si覆盖层111a 因为发射极形成在p + 1 Si 1-x Ge层上。发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的N +和/或多个多晶硅层129b组成，在基底开口118中的Si覆盖层111a上形成含有高浓度的磷的多晶硅层129a。通过抑制Si覆盖层111a的基底层中的杂质浓度分布适当地保持以过高浓度的磷（P）掺杂。 Si覆盖层111a的上部可以含有p型杂质。因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

36. 发明授权

US06847062B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06847062B2
公开(公告)日：2005-01-25
申请号：US10413305
申请日：2003-04-15
申请人： Teruhito Ohnishi , Koichiro Yuki , Shigeki Sawada , Keiichiro Shimizu , Koichi Hasegawa , Tohru Saitoh
发明人： Teruhito Ohnishi , Koichiro Yuki , Shigeki Sawada , Keiichiro Shimizu , Koichi Hasegawa , Tohru Saitoh
IPC分类号： H01L21/331 , H01L29/737 , H01L31/0328 , H01L29/00
CPC分类号： H01L29/66242 , H01L29/7378
摘要： In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.
摘要翻译：在用作SiGeC-HBT的半导体器件中，在Si外延生长层2上形成发射极/基极层叠部分20.发射极/基极层叠部分20包括：SiGeC间隔层21; 含有高浓度硼的SiGeC芯基层22，SiGe覆盖层23; Si覆盖层24和通过将磷引入Si覆盖层24和SiGe覆盖层23而形成的发射极层25。

37. 发明授权

US06399993B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06399993B1
公开(公告)日：2002-06-04
申请号：US09786551
申请日：2001-03-07
申请人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
发明人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
IPC分类号： H01L2972
CPC分类号： H01L21/76237 , H01L21/8249
摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.
摘要翻译：在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

38. 发明授权

US06214126B1 Method for cleaning a silicon substrate 失效
标题翻译：清洗硅基板的方法
公开(公告)号：US06214126B1
公开(公告)日：2001-04-10
申请号：US08744688
申请日：1996-11-07
申请人： Yuichi Miyoshi , Michikazu Matsumoto , Teruhito Ohnishi
发明人： Yuichi Miyoshi , Michikazu Matsumoto , Teruhito Ohnishi
IPC分类号： C23G2300
CPC分类号： H01L21/02052 , Y10S134/902
摘要： A silicon substrate is cleaned using a liquid mixture primarily containing ammonia and hydrogen peroxide. A liquid containing ammonia is added to the liquid mixture to maintain the concentration of ammonia in the liquid mixture applied to the silicon substrate in the range between 2.5 wt. % and 3.5 wt. %. The liquid containing ammonia is added to the liquid mixture at a constant time interval. The constant time interval is set to be equal to a time period which is necessary for the concentration of ammonia in the liquid mixture to change from a first concentration level of no more than 3.5 wt. % to a second concentration level of no less than 2.5 wt. %, the second concentration level being lower than the first concentration level. The concentration of ammonia in the liquid containing ammonia and the amount thereof to be added to the liquid mixture are adjusted so as to increase the concentration of ammonia in the liquid mixture to the first concentration level by addition thereof.
摘要翻译：使用主要含有氨和过氧化氢的液体混合物清洁硅衬底。将含有氨的液体加入到液体混合物中，以将液体混合物中的氨的浓度保持在硅衬底上，其浓度在2.5wt。％和3.5wt。％。将含有氨的液体以恒定的时间间隔加入到液体混合物中。将恒定时间间隔设定为等于液体混合物中的氨浓度从不超过3.5重量％的第一浓度水平变化所需的时间段。％至第二浓度水平不低于2.5wt。％，第二浓度水平低于第一浓度水平。调节含氨液体中的氨浓度和加入到液体混合物中的量，以便通过添加将液体混合物中的氨浓度提高到第一浓度水平。

39. 发明授权

US5472826A Semiconductor device fabrication method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5472826A
公开(公告)日：1995-12-05
申请号：US193550
申请日：1994-02-08
申请人： Masayuki Endo , Teruhito Ohnishi , Noboru Nomura
发明人： Masayuki Endo , Teruhito Ohnishi , Noboru Nomura
IPC分类号： G03F7/38 , H01L21/027 , H01L21/266 , H01L21/30 , H01L21/311 , G03F7/26
CPC分类号： H01L21/31111 , H01L21/0274 , H01L21/266
摘要： An improved semiconductor device fabrication technique is disclosed. A resist layer, composed of a chemical compound which generates an acid when exposed to energy light and a resin which contains protecting groups that are removed from the resin by acid, is formed on top of a semiconductor substrate. The resist layer is subjected to a lithography and a development process and is formed into a resist pattern. This resist pattern is exposed to ultraviolet beams, and the chemical compound generates an acid and the protecting groups are removed from the resin. As a result of such an elimination reaction, the surface of the resist pattern becomes coarse. Thereafter, an implant of ions is carried out to the semiconductor substrate using the resist pattern as a mask. The surface of the semiconductor substrate is cleaned using a cleaning solution, and the resist pattern with a coarse surface can easily and completely be removed from the semiconductor substrate.
摘要翻译：公开了一种改进的半导体器件制造技术。在半导体基板的顶部形成有由暴露于能量光时产生酸的化合物构成的抗蚀剂层和含有通过酸从树脂中除去的保护基的树脂。对抗蚀剂层进行光刻和显影处理，并形成抗蚀剂图案。该抗蚀剂图案暴露于紫外线，并且化合物产生酸，并且保护基团从树脂中除去。作为这种消除反应的结果，抗蚀图案的表面变粗。此后，使用抗蚀剂图案作为掩模，对半导体衬底进行离子注入。使用清洗液对半导体基板的表面进行清洗，可以容易且完全地从半导体基板除去具有粗糙表面的抗蚀剂图案。

40. 发明授权

US5449934A Semiconductor memory device and process 失效
标题翻译：半导体存储器件和工艺
公开(公告)号：US5449934A
公开(公告)日：1995-09-12
申请号：US235710
申请日：1994-04-29
申请人： Tomofumi Shono , Teruhito Ohnishi , Masanori Fukumoto
发明人： Tomofumi Shono , Teruhito Ohnishi , Masanori Fukumoto
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8246 , H01L23/532 , H01L27/105 , H01L27/108 , H01L27/02 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53219 , H01L23/53223 , H01L23/53257 , H01L27/10808 , H01L2924/0002
摘要： A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.
摘要翻译：提供了具有存储电容器的半导体存储器件，其具有大的存储容量以及高的组件密度，并且便于生产。在半导体衬底中局部形成开关晶体管。在晶体管上形成的是设置在其上的存储电容器的上层电线。存储电容器触点通过上层导线。在确保存储电容器接触的良好容量的同时，也可以在将上层电线的图案同时传送到存储单元区域以及外围电路区域上时，可以有利地获得焦点的允许。特别地，通过使存储电容器的触点通过位线，漏极和源极可以与字线对称地布置，如具有位线存储 - 电容器组织单元的存储单元。这消除了过多的部分，导致密度增加。

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