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31. 发明授权

US08209581B2 Receiving apparatus and method and program for receiving and decoding a low density parity check code 有权
标题翻译：用于接收和解码低密度奇偶校验码的接收装置和方法和程序
公开(公告)号：US08209581B2
公开(公告)日：2012-06-26
申请号：US12253347
申请日：2008-10-17
申请人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
发明人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
IPC分类号： G06F11/00
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.
摘要翻译：一种接收装置，包括：LDPC解码器，被配置为解码所述数据信号和所述传输控制信号;数据信号输入缓冲器，布置在所述LDPC解码器之前并被配置为保持所述接收的数据信号;以及传输控制信号输入缓冲器， LDPC解码器，被配置为保持所接收的发送控制信号，以及控制器，被配置为选择保持在数据信号输入缓冲器中的数据信号中的一个和保持在发送控制信号输入缓冲器中的发送控制信号作为经解码的信号;以及将所选择的信号发送到LDPC解码器，以使LDPC解码器对经过解码的信号进行解码。

32. 发明授权

US08010870B2 Coding apparatus and coding method 有权
标题翻译：编码装置及编码方法
公开(公告)号：US08010870B2
公开(公告)日：2011-08-30
申请号：US11912485
申请日：2005-04-25
申请人： Takashi Yokokawa , Makiko Yamamoto , Misa Nakane
发明人： Takashi Yokokawa , Makiko Yamamoto , Misa Nakane
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1137 , H03M13/116 , H03M13/1185 , H03M13/6502 , H03M13/6516 , H03M13/6561
摘要： The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder 13 integrates the product of an information word D13 of six bits supplied from a cyclic shift circuit 12 and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15 to a RAM 14. The RAM 14 stores the sum D15. Further, the RAM 14 successively reads out sums D16 of 2 bits stored already therein and supplies the read out sums D16 as sums D17 to an accumulator 16 through an interleaver 15. The accumulator 16 integrates the sums D17 and outputs a sum D18 obtained as a result of the integration as a parity bit p of a codeword c through a selector 17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.
摘要翻译：本发明涉及一种可以在不改变线性码的编码中的操作速度的情况下减小电路规模的编码装置和编码方法。加法器13将从循环移位电路12提供的六位的信息字D13和对应于每行的信息的检查矩阵H的信息部分的乘积以六行的单位积分，并将积分值作为总和D15到RAM14.RAM14存储总和D15。此外，RAM14连续地读出其中已经存储的2位的和D16，并通过交织器15将累加器D16作为和D17提供给累加器16.累加器16对和D17进行积分，并输出作为作为通过选择器17的码字c的奇偶校验位p的积分的结果。本发明可以应用于发送卫星广播的广播站的装置。

33. 发明申请

US20110164703A1 RECEPTION APPARATUS AND METHOD, PROGRAM AND RECEPTION SYSTEM 有权
标题翻译：接收装置和方法，程序和接收系统
公开(公告)号：US20110164703A1
公开(公告)日：2011-07-07
申请号：US12981948
申请日：2010-12-30
申请人： Takashi Yokokawa , Satoshi Okada
发明人： Takashi Yokokawa , Satoshi Okada
IPC分类号： H04B1/06
CPC分类号： H04L27/2647 , H04H40/18 , H04H60/40 , H04N21/235 , H04N21/23608 , H04N21/2383 , H04N21/242 , H04N21/4302 , H04N21/4305 , H04N21/434 , H04N21/4344 , H04N21/4345 , H04N21/435 , H04N21/4382 , H04W56/00 , H04W56/001 , H04W56/003
摘要： Disclosed herein is a reception apparatus, including: a reception section configured to receive an OFDM (Orthogonal Frequency Division Multiplexed) signal obtained by modulating a common packet sequence configured from a packet common to streams and a data packet sequence configured from packets individually unique to the streams; a time counting section configured to count, using predetermined time indicated by additional information added to particular packets of the common and data packet sequences obtained by demodulating the received OFDM signal as a reference, elapsed time after the predetermined time; a detection section configured to compare the counted time and time indicated by the additional information added to the particular packets of the common and data packet sequences to detect a displacement in the time direction between the packets; and a correction section configured to correct the displacement between the packets of the common and data packet sequences in the time direction.
摘要翻译：这里公开了一种接收装置，包括：接收部分，被配置为接收通过调制由流公用的分组配置的公共分组序列获得的OFDM（正交频分复用）信号，以及从由溪流时间计数部分，被配置为使用通过将通过解调所接收的OFDM信号作为参考获得的公共数据分组序列的特定分组附加的附加信息指定的预定时间进行计数，经过预定时间之后的经过时间; 检测部，被配置为比较由附加到所述公用数据包序列和所述数据包序列的特定分组的附加信息所指示的所计算的时间和时间，以检测所述分组之间的时间方向上的位移; 以及校正部，被配置为在时间方向上校正公用数据包序列和数据包序列的包之间的位移。

34. 发明申请

US20100269019A1 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20100269019A1
公开(公告)日：2010-10-21
申请号：US12743398
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Ryoji Ikegaya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L27/2647 , H03M13/033 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/356 , H03M13/6552 , H03M13/6555
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.
摘要翻译：数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。本发明可以应用于例如用于发送LDPC码等的传输系统。

35. 发明申请

US20080168333A1 DECODING METHOD AND DECODING APPARATUS AS WELL AS PROGRAM 有权
标题翻译：解码方法和解码设备作为程序
公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
申请人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
发明人： Makiko YAMAMOTO , Satoshi Okada , Toshiyuki Miyauchi , Takashi Yokokawa
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译：一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

36. 发明申请

US20060242536A1 Decoding device and decoding method 失效
标题翻译：解码设备和解码方法
公开(公告)号：US20060242536A1
公开(公告)日：2006-10-26
申请号：US11409237
申请日：2006-04-24
申请人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
发明人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： The present invention provides a decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device include: a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value. In processing performed as the check node operation and the variable node operation, the first operation unit and the second operation unit use the second quantization value in processing from after the operation of the nonlinear function to the operation of the inverse function, and use the first quantization value in the other processing.
摘要翻译：本发明提供一种用于解码LDPC（低密度奇偶校验）码的解码装置。解码装置包括：第一操作单元，用于执行用于解码LDPC码的校验节点操作，该操作包括非线性函数的操作和非线性函数的反函数的操作; 以及第二操作单元，用于执行用于对LDPC码进行解码的可变节点操作。第一操作单元包括：第一转换单元，用于将分配给数值的第一量化值转换成表示具有比第一量化值更高的精度的数值的第二量化值;以及第二转换单元，用于将第二量化值进入第一个量化值。在作为校验节点操作和可变节点操作执行的处理中，第一操作单元和第二操作单元使用从非线性函数操作之后的处理中的第二量化值到逆函数的操作，并且使用第一操作单元其他处理中的量化值。

37. 发明申请

US20050010848A1 Encoding device, encoding method, encoding method program, decoding device, decoding method, decoding method program 失效
标题翻译：编码装置，编码方法，编码方法程序，解码装置，解码方法，解码方法程序
公开(公告)号：US20050010848A1
公开(公告)日：2005-01-13
申请号：US10498936
申请日：2003-10-08
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Yasuhiro Iida , Kohei Yamamoto , Masayuki Hattori
IPC分类号： G06F11/10 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/00
CPC分类号： H04L1/006 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/29 , H03M13/2972 , H04L1/0055 , H04L1/0065 , H04L1/0071
摘要： The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.
摘要翻译：本发明特别适用于串联编码和串行级联网格编码调制。在作为内部编码的第二编码器107中，输出未被编码或编码以产生有限脉冲响应的序列和被编码以产生无限脉冲响应的序列。在第二编码107之前的交织106中，将这些序列置换为不相互混合。

38. 发明授权

US09106256B2 Data processing device and data processing method for encoding/decoding information bits 有权
标题翻译：用于对信息位进行编码/解码的数据处理装置和数据处理方法
公开(公告)号：US09106256B2
公开(公告)日：2015-08-11
申请号：US13818709
申请日：2011-08-25
申请人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/00 , H03M13/05 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04L27/36 , H03M13/15
CPC分类号： H03M13/05 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L27/36
摘要： A data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals.
摘要翻译：一种数据处理装置和数据处理方法，能够提高数据的误差抵抗能力。 LDPC编码器使用码长为4320位的LDPC码和包括½，7/12，⅔，¾的四种类型之一的编码速率来执行编码。通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置根据每72列的码长和编码速率在72列的列方向上的信息长度。奇偶校验矩阵初始值表例如用于移动终端的数字广播。

39. 发明授权

US09094043B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09094043B2
公开(公告)日：2015-07-28
申请号：US13982494
申请日：2012-02-01
申请人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/00 , H03M13/09 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/15 , H04L27/26
CPC分类号： H03M13/09 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0072 , H04L27/2626 , H04L27/2647
摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
摘要翻译：一种数据处理装置和能够改善抵抗误差的数据处理方法。具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。本技术可以应用于例如LDPC码的传输。

40. 发明申请

US20130342764A1 SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND PROGRAM 有权
标题翻译：信号处理设备，信号处理方法和程序
公开(公告)号：US20130342764A1
公开(公告)日：2013-12-26
申请号：US14002996
申请日：2012-03-01
申请人： Takashi Yokokawa , Lachlan Bruce Michael , Yuken Goto , Kenichi Kobayashi
发明人： Takashi Yokokawa , Lachlan Bruce Michael , Yuken Goto , Kenichi Kobayashi
IPC分类号： H04N5/455
CPC分类号： H04N5/455 , H04L27/2647 , H04L65/00 , H04N21/4382 , H04N21/6112
摘要： The present technology relates to a signal processing device, a signal processing method, and a program capable of appropriately demodulating a desired signal from a multiplexed signal obtained by multiplexing a plurality of signals. A preamble signal is detected from a multiplexed signal obtained by multiplexing a plurality of signals. When information for discriminating each of the signals that is contained in the preamble signal indicates a first signal, demodulation by a demodulator is continued and the first signal is demodulated. When information for discriminating each of the signals that is contained in the preamble signal indicates a second signal, demodulation is not performed by stopping the demodulation by the demodulator. The present technology can be applied to a signal processing device that processes signals for digital broadcasting.
摘要翻译：本技术涉及一种信号处理装置，信号处理方法以及能够从通过复用多个信号而获得的复用信号适当地解调所需信号的程序。从通过复用多个信号获得的多路复用信号检测前导信号。当用于识别前导信号中包含的每个信号的信息指示第一信号时，解调器继续进行解调，并解调第一信号。当用于识别前导信号中包含的每个信号的信息指示第二信号时，不通过解调器停止解调来执行解调。本技术可以应用于处理用于数字广播的信号的信号处理装置。

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