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31. 发明授权

US08907420B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08907420B2
公开(公告)日：2014-12-09
申请号：US12789008
申请日：2010-05-27
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/66 , H01L29/78 , H01L29/94 , H01L29/10 , H01L29/08 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

32. 发明授权

US07541643B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07541643B2
公开(公告)日：2009-06-02
申请号：US11399448
申请日：2006-04-07
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11
摘要翻译：该半导体器件包括：交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。在器件区域和端部区域的相同深度位置处，器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于加或减5％。器件区域中的第一半导体柱层的宽度W11 [μm]，器件区域中的第二半导体柱层的宽度W21 [μm]，端部区域中的第一半导体柱层的宽度W12 [μm] ，并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11

33. 发明申请

US20080135926A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080135926A1
公开(公告)日：2008-06-12
申请号：US11936412
申请日：2007-11-07
申请人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L27/06
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0696 , H01L29/1095
摘要： A semiconductor device includes: a drift layer having a superjunction structure; a semiconductor base layer selectively formed in a part of one surface of the drift layer; a first RESURF layer formed around a region having the semiconductor base layer formed thereon; a second semiconductor RESURF layer of a conductivity type which is opposite to a conductivity type of the first semiconductor RESURF layer; a first main electrode connected to a first surface of the drift layer; and a second main electrode connected to a second surface of the drift layer. The first RESURF layer is connected to the semiconductor base layer. The second semiconductor RESURF layer is in contact with the first semiconductor RESURF layer.
摘要翻译：一种半导体器件包括：具有超结构结构的漂移层; 选择性地形成在所述漂移层的一个表面的一部分中的半导体基层; 在其上形成有半导体基底层的区域周围形成的第一RESURF层; 与第一半导体RESURF层的导电类型相反的导电类型的第二半导体RESURF层; 连接到所述漂移层的第一表面的第一主电极; 以及连接到漂移层的第二表面的第二主电极。第一RESURF层连接到半导体基层。第二半导体RESURF层与第一半导体RESURF层接触。

34. 发明申请

US20070267664A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070267664A1
公开(公告)日：2007-11-22
申请号：US11751244
申请日：2007-05-21
申请人： Yasuto SUMI , Masakatsu Takashita , Masaru Izumisawa , Hiroshi Ohta , Wataru Saito , Syotaro Ono
发明人： Yasuto SUMI , Masakatsu Takashita , Masaru Izumisawa , Hiroshi Ohta , Wataru Saito , Syotaro Ono
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L23/544 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a first semiconductor layer of the first conductivity type. A pillar layer includes first semiconductor pillars of the first conductivity type and second semiconductor pillars of the second conductivity type arranged periodically and alternately on the first semiconductor layer. The first and second semiconductor pillar layer have a cross section in the shape of stripes in a planar direction. There is a semiconductor base layer of the second conductivity type selectively formed in a surface of the second semiconductor pillar, and a semiconductor diffusion layer of the first conductivity type selectively formed in a surface of the semiconductor base layer. The longitudinal direction of the shape of stripes is made almost same as the direction of pattern shift caused in the first semiconductor layer.
摘要翻译：根据本发明的半导体器件包括第一导电类型的第一半导体层。柱层包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱，其周期性和交替地布置在第一半导体层上。第一和第二半导体柱层在平面方向上具有条状的横截面。存在选择性地形成在第二半导体柱的表面中的第二导电类型的半导体基底层和选择性地形成在半导体基底层的表面中的第一导电类型的半导体扩散层。条纹形状的纵向方向与第一半导体层中引起的图案偏移的方向几乎相同。

35. 发明申请

US20070018243A1 Semiconductor element and method of manufacturing the same 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US20070018243A1
公开(公告)日：2007-01-25
申请号：US11485284
申请日：2006-07-13
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.
摘要翻译：提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

36. 发明授权

US08772869B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08772869B2
公开(公告)日：2014-07-08
申请号：US12050405
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono
发明人： Wataru Saito , Syotaro Ono
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7811
摘要： A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.
摘要翻译：功率半导体器件包括：第一半导体层; 第二和第三半导体层，并且沿着平行于第一半导体层的上表面的方向排列; 以及多个第四半导体层，设置在第三半导体层的一些上部区域上。第四半导体层的阵列周期大于第二半导体层的阵列周期。在第四半导体层之间的中心部分的直接上部区域中的栅极绝缘膜的一部分的厚度比在第四半导体层的直接上部区域中的栅极绝缘膜的一部分的厚度厚。第二半导体层和第三半导体层在中心部分的片状杂质浓度高于第四半导体层的紧邻下部区域中的第三半导体层的片状杂质浓度。

37. 发明授权

US08058688B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08058688B2
公开(公告)日：2011-11-15
申请号：US11864101
申请日：2007-09-28
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L31/119
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; a plurality of second semiconductor column regions of a second conductivity type provided on the first semiconductor layer, the second semiconductor column regions being adjacent to the first semiconductor column regions; a first semiconductor region; a second semiconductor region; a gate insulating film; a first main electrode; a second main electrode; and a control electrode. Doping concentrations in both the first and second semiconductor column region are low on the near side of the first semiconductor layer and high on the second main electrode side.
摘要翻译：半导体器件包括：半导体衬底; 第一导电类型的第一半导体层设置在半导体衬底的主表面上并且具有比半导体衬底低的掺杂浓度; 设置在第一半导体层上的多个第一导电类型的第一半导体柱区域; 设置在所述第一半导体层上的第二导电类型的多个第二半导体柱区域，所述第二半导体柱区域与所述第一半导体柱区域相邻; 第一半导体区域; 第二半导体区域; 栅极绝缘膜; 第一主电极; 第二主电极; 和控制电极。第一和第二半导体柱区域中的掺杂浓度在第一半导体层的近侧为低，在第二主电极侧为高。

38. 发明授权

US07812392B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07812392B2
公开(公告)日：2010-10-12
申请号：US12138875
申请日：2008-06-13
申请人： Wataru Saito , Syotaro Ono
发明人： Wataru Saito , Syotaro Ono
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741
摘要： A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a horizontal direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer, and a sixth semiconductor layer located outside and adjacent to the periodic array structure of the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and having a lower impurity concentration than the periodic array structure. The amount of impurity in the outermost semiconductor layer of the first conductivity type or the second conductivity type adjacent to the sixth semiconductor layer in the periodic array structure is generally half the amount of impurity in the second first-conductivity-type semiconductor layer or the third second-conductivity-type semiconductor layer inside the outermost semiconductor layer.
摘要翻译：半导体器件包括第一第一导电型半导体层，设置在第一第一导电型半导体层的主表面上的第二第一导电型半导体层; 与所述第二第一导电型半导体层相邻的第三第二导电型半导体层，设置在所述第一第一导电型半导体层的主表面上，并且与所述第二第一导电型半导体层的第二第一导电型半导体层在与第一第一导电型半导体层的主表面大致平行的水平方向上的第一导电型半导体层以及与第二第一导电型半导体的周期性阵列结构的外侧相邻的第六半导体层层和第三第二导电型半导体层，设置在第一第一导电型半导体层的主表面上，并且具有比周期性阵列结构低的杂质浓度。在周期性排列结构中与第六半导体层相邻的第一导电类型或第二导电类型的最外半导体层中的杂质的量通常为第二第一导电型半导体层或第三导电型半导体层中杂质的量的一半第二导电型半导体层。

39. 发明授权

US07800175B2 Vertical power semiconductor device with high breakdown voltage corresponding to edge termination and device regions 失效
标题翻译：具有高击穿电压的垂直功率半导体器件对应于边缘终端和器件区域
公开(公告)号：US07800175B2
公开(公告)日：2010-09-21
申请号：US12243280
申请日：2008-10-01
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/404
摘要： A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region.
摘要翻译：半导体装置包括：第一导电类型的半导体层; 设置在所述半导体层的前侧的第一主电极; 设置在所述半导体层的背面的第二主电极，所述背面与所述前侧相反; 在第一主电极和第二主电极之间沿垂直方向形成有主电流路径的器件区域外的边缘终端区域的半导体层的表面部分中设置的多个第二导电类型的半导体区域 ; 以及设置在边缘终端区域中的半导体层中的与半导体区域间隔开并且彼此间隔开的第二导电类型的多个掩埋半导体区域。基本上与半导体层的前侧相同的深度设置的掩埋半导体区域被编号为第一，第二。。。第n个从靠近器件区的一个顺序地，与半导体层的前侧不同的深度设置的第n个埋入半导体区域相对于相应的第n个半导体区域朝向器件区域移位，位于半导体层的前侧较深的掩埋半导体区域朝向器件区域更大地移位。

40. 发明申请

US20100230750A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100230750A1
公开(公告)日：2010-09-16
申请号：US12789008
申请日：2010-05-27
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

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