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31. 发明授权

US08168492B2 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 有权
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US08168492B2
公开(公告)日：2012-05-01
申请号：US12754128
申请日：2010-04-05
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L21/8238
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

32. 发明授权

US07871875B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07871875B2
公开(公告)日：2011-01-18
申请号：US12662083
申请日：2010-03-30
申请人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
发明人： Sung-Min Kim , Min-Sang Kim , Ji-Myoung Lee , Dong-Won Kim
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7856 , H01L29/4925 , H01L29/4958 , H01L29/66795
摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.
摘要翻译：提供FinFET及其制造方法。 FinFET可以包括至少一个有源鳍片，至少一个栅极绝缘层图案，第一电极图案，第二电极图案和至少一对源极/漏极扩展区域。所述至少一个活性翅片可以形成在基底上。至少一个栅极绝缘层图案可以形成在至少一个活性鳍上。第一电极图案可以形成在至少一个栅极绝缘层图案上。此外，第一电极图案可以与至少一个活性鳍相交。第二电极图案可以形成在第一电极图案上。此外，第二电极图案可以具有大于第一电极图案的宽度的宽度。至少一对源极/漏极扩展区域可以形成在第一电极图案的两侧上的至少一个有源鳍片的表面上。因此，FinFET可能具有改进的容量和减小的GIDL电流。

33. 发明授权

US07790494B2 Method of fabricating a multi-bit electro-mechanical memory device 有权
标题翻译：制造多位机电存储器件的方法
公开(公告)号：US07790494B2
公开(公告)日：2010-09-07
申请号：US12007819
申请日：2008-01-16
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
IPC分类号： H01L21/00 , H01L35/24 , H01L51/00 , H01L29/792
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L29/0665 , H01L29/0673
摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.
摘要翻译：存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。位线可以在第一方向上形成在基板上。第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

34. 发明授权

US07473963B2 Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管
公开(公告)号：US07473963B2
公开(公告)日：2009-01-06
申请号：US11854734
申请日：2007-09-13
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

35. 发明申请

US20080185668A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080185668A1
公开(公告)日：2008-08-07
申请号：US12007819
申请日：2008-01-16
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Dong-Gun Park
IPC分类号： H01L29/84 , H01L21/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L29/0665 , H01L29/0673
摘要： A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.
摘要翻译：存储器件可以包括衬底，位线，至少第一下部字线，至少第一陷阱位置，焊盘电极，至少第一悬臂电极和/或至少第一上部字线。位线可以在第一方向上形成在基板上。第一下部字线和第一陷阱位置可以与位线绝缘并且沿与该位线交叉的第二方向形成。焊盘电极可以在第一下字线和第一陷阱位置的侧壁处绝缘并连接到位线。第一悬臂电极可以形成在第一方向上，连接到焊盘电极，浮在第一陷阱位置上，具有至少第一下部空的空间，和/或构造成沿第三方向弯曲。第一上部字线可以在第二方向上的第一悬臂电极上形成有至少第一上部空置空间。

36. 发明申请

US20100197099A1 SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：肖特基屏障器件及其制造方法
公开(公告)号：US20100197099A1
公开(公告)日：2010-08-05
申请号：US12759290
申请日：2010-04-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

37. 发明授权

US07662720B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07662720B2
公开(公告)日：2010-02-16
申请号：US12111633
申请日：2008-04-29
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L21/311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

38. 发明授权

US07382018B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07382018B2
公开(公告)日：2008-06-03
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

39. 发明申请

US20080093664A1 Memory device and method of manufacturing the same 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：US20080093664A1
公开(公告)日：2008-04-24
申请号：US11894449
申请日：2007-08-21
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Dong-Won Kim , Sung-Hwan Kim
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Dong-Won Kim , Sung-Hwan Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42356 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7881 , H01L29/7926
摘要： In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending between the first gate electrode and the second gate electrode. The first gate electrode is used for removing a charge trapped in the second gate insulating layer. Thus, the memory device can have an improved characteristic when performing an erase operation.
摘要翻译：在存储器件和存储器件的制造方法中，存储器件包括由第一栅极绝缘层包围的第一栅极电极，由可以是ONO层的第二栅极绝缘层包围的第二栅电极，以及通道在第一栅电极和第二栅电极之间垂直延伸的区域。第一栅电极用于去除在第二栅极绝缘层中俘获的电荷。因此，当执行擦除操作时，存储器件可以具有改进的特性。

40. 发明申请

US20070111435A1 Schottky barrier finfet device and fabrication method thereof 有权
标题翻译：肖特基势垒鳍片器件及其制造方法
公开(公告)号：US20070111435A1
公开(公告)日：2007-05-17
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336 , H01L29/76 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

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