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31. 发明授权

US07734897B2 Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads 有权
标题翻译：在具有多个执行线程的超标量数据处理装置和方法中，将存储器访问操作分配给具有存储器访问能力的管线
公开(公告)号：US07734897B2
公开(公告)日：2010-06-08
申请号：US11312653
申请日：2005-12-21
申请人： David Hennah Mansell
发明人： David Hennah Mansell
IPC分类号： G06F15/76
CPC分类号： G06F9/3851 , G06F9/3822 , G06F9/3824 , G06F9/3885 , G06F9/3891 , G06F12/0846 , G06F12/0864
摘要： A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline. Such a system has been found to provide an effective balance between increasing the efficiency of operation of the superscalar data processing apparatus when employing multiple execution threads whilst also alleviating the need for complex hardware to handle hazard detection.
摘要翻译：提供了一种用于处理操作的超标量数据处理装置和方法，该装置具有多个执行线程，每个执行线程可操作以处理包括至少一个存储器访问操作的一系列操作。超标量数据处理装置包括用于执行操作的多个执行流水线，并发出用于将每个操作分配给一个执行流水线以供该执行流水线执行的逻辑。至少两个执行管线是能够执行存储器访问操作的能够存储器访问的管线，并且每个具有存储器访问能力的流水线与多个执行线程的子集相关联。为每个执行线程安排问题逻辑，以将该执行线程的任何存储器访问操作分配给相关的存储器访问能力管线。已经发现，这种系统在采用多个执行线程时提高超标量数据处理装置的操作效率之间的有效平衡，同时还减少了复杂硬件处理危险检测的需要。

32. 发明授权

US07661104B2 Task following between multiple operating systems 有权
标题翻译：多个操作系统之间的任务
公开(公告)号：US07661104B2
公开(公告)日：2010-02-09
申请号：US10714482
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00 , H04L29/06
CPC分类号： G06F9/4812 , G06F9/526
摘要： A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
摘要翻译：处理器可以利用两个可以进行呼叫的操作系统（非安全的，安全的）。为了使第二操作系统能够跟踪由第一操作系统进行的任务切换，每次对第二操作系统进行呼叫时，该呼叫包括标识符，以便能够在第一操作系统上执行的任务之间进行区分，那个电话是做的。标识符可以是呼叫标识符和/或目标线程标识符，并且可以包括其他参数。

33. 发明授权

US07529916B2 Data processing apparatus and method for controlling access to registers 有权
标题翻译：用于控制对寄存器的访问的数据处理装置和方法
公开(公告)号：US07529916B2
公开(公告)日：2009-05-05
申请号：US11504780
申请日：2006-08-16
申请人： Daniel Kershaw , James Ian McNiven , Daniel Luke Kefford , David Hennah Mansell
发明人： Daniel Kershaw , James Ian McNiven , Daniel Luke Kefford , David Hennah Mansell
IPC分类号： G06F9/00
CPC分类号： G06F9/45533 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/462 , G06F9/468 , G06F9/4812 , G06F21/74
摘要： A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data values, the processing unit having a plurality of modes of operation. A plurality of registers are provided for storing data values for access by the processing unit, with a subset of those registers being mode specific registers. Each mode specific register is used by the processing unit when operating in an associated mode of operation. The processing unit is switchable between a plurality of contexts, the data values stored in the plurality of registers being dependent on a current context of the processing unit. The processing unit performs a switch operation to switch from the current context to a new context, during which the data values in the registers are updated having regard to the new context. A control register is provided which, for at least one mode of operation having at least one mode specific register associated therewith, has an access field which is programmable by the processing unit when operating in a predetermined mode of operation. When the access field is set, the processing unit is selectively denied access to the associated at least one mode specific register, whereby updating of the data values in the associated at least one mode specific register is avoided during the switch operation. This significantly increases the speed of the switch operation.
摘要翻译：提供了一种用于控制对寄存器的访问的数据处理装置和方法。数据处理装置包括用于对数据值执行数据处理操作的处理单元，所述处理单元具有多种操作模式。提供多个寄存器用于存储用于由处理单元访问的数据值，其中这些寄存器的子集是模式特定寄存器。当在相关联的操作模式下操作时，处理单元使用每个模式特定寄存器。处理单元可在多个上下文之间切换，存储在多个寄存器中的数据值取决于处理单元的当前上下文。处理单元执行切换操作以从当前上下文切换到新的上下文，在此期间，考虑到新的上下文，更新寄存器中的数据值。提供控制寄存器，对于具有与其相关联的至少一个模式特定寄存器的至少一种操作模式，具有在以预定操作模式操作时由处理单元可编程的访问字段。当访问字段被设置时，处理单元被选择性地拒绝对相关联的至少一个模式特定寄存器的访问，由此在切换操作期间避免在相关联的至少一个模式特定寄存器中更新数据值。这显着提高了开关操作的速度。

34. 发明授权

US07185159B2 Technique for accessing memory in a data processing apparatus 有权
标题翻译：用于访问数据处理设备中的存储器的技术
公开(公告)号：US07185159B2
公开(公告)日：2007-02-27
申请号：US10714520
申请日：2003-11-17
申请人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
发明人： Lionel Beinet , David Hennah Mansell , Simon Charles Watt
IPC分类号： G06F12/00
CPC分类号： G06F21/85 , G06F12/1491 , G06F21/629 , G06F21/74 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain. The presence of this domain signal issued as part of the memory access request enables checking to be performed to ensure that secure data within the secure memory is not accessed by the device when the memory access request pertains to the non-secure domain.
摘要翻译：本发明提供一种访问存储器的数据处理装置和方法。数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。数据处理设备包括经由设备总线与存储器耦合的设备，当设备需要存储器中的数据项时，该设备可操作地向设备总线发出与安全性相关的存储器访问请求域或非安全域。存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。根据本发明，由设备发布的存储器访问请求包括识别存储器访问请求是否属于安全域或非安全域的域信号。作为存储器访问请求的一部分而发布的该域信号的存在使得能够执行检查，以便当存储器访问请求与非安全域相关时，确保安全存储器内的安全数据不被设备访问。

35. 发明授权

US07305534B2 Control of access to a memory by a device 有权
标题翻译：控制设备对存储器的访问
公开(公告)号：US07305534B2
公开(公告)日：2007-12-04
申请号：US10714561
申请日：2003-11-17
申请人： Simon Charles Watt , Lionel Belnet , David Hennah Mansell , Nicolas Chaussade , Peter Guy Middleton
发明人： Simon Charles Watt , Lionel Belnet , David Hennah Mansell , Nicolas Chaussade , Peter Guy Middleton
IPC分类号： G06F12/00
CPC分类号： G06F12/1491 , G06F21/6218 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/85 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.
摘要翻译：本发明提供一种用于控制对存储器的访问的数据处理装置和方法。数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。数据处理装置包括经由设备总线耦合到存储器的设备，并且当设备需要存储器中的数据项时，可以向设备总线发出存储器访问请求，该存储器访问请求涉及安全域或非安全域。存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。根据本发明，数据处理装置还包括耦合到设备总线的分区检查逻辑，每当由设备发布的存储器访问请求与非安全域相关时，可操作，以检测存储器访问请求是否正在寻找以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。这种方法显着提高了包含在存储器安全部分内的数据的安全性。

36. 发明授权

US07149862B2 Access control in a data processing apparatus 有权
标题翻译：数据处理装置中的访问控制
公开(公告)号：US07149862B2
公开(公告)日：2006-12-12
申请号：US10933478
申请日：2004-09-03
申请人： Andrew David Tune , Peter James Aldworth , Simon Charles Watt , Lionel Belnet , David Hennah Mansell
发明人： Andrew David Tune , Peter James Aldworth , Simon Charles Watt , Lionel Belnet , David Hennah Mansell
IPC分类号： G06F12/00
CPC分类号： G06F12/1441
摘要： A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request. Further, access control logic is provided which is associated with the slave device, the access control logic being operable to receive the access request from the bus and an indication of the partition from the control storage and, if the access request is a non-secure access request, to prevent access to the secure region.
摘要翻译：提供了一种用于控制对从设备的访问的数据处理设备和方法，该从设备具有与之相关联的地址范围。该装置包括可编程的控制存储器，用于定义识别地址范围中的安全区域和非安全区域的分区，数据处理设备支持包括安全模式的多种操作模式，并且控制存储器仅可由软件在安全模式下执行。主设备被布置为在总线上发出访问请求，该访问请求标识地址范围内的一系列地址，并且包括指示该访问请求是安全访问请求还是非安全访问请求的控制信号。安全区域只能通过安全访问请求访问。此外，提供与从设备相关联的访问控制逻辑，访问控制逻辑可操作以从总线接收访问请求以及来自控制存储器的分区的指示，以及如果访问请求是非安全的访问请求，以防止访问安全区域。

37. 发明授权

US07124274B2 Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain 有权
标题翻译：具有安全域和非安全域的系统内的虚拟到物理内存地址映射
公开(公告)号：US07124274B2
公开(公告)日：2006-10-17
申请号：US10714560
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Michael Robert Nonweiler
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Michael Robert Nonweiler
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F9/4812 , G06F12/1009 , G06F12/1027 , G06F21/74 , G06F2209/481
摘要： An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
摘要翻译：一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器和安全域或非安全域，所述安全域或非安全域包括作为安全域中的模式的至少一个安全模式; 并且至少一个非安全模式是非安全域中的模式。当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。处理器还包括分别在非安全和安全域中操作的非安全转换表基地址寄存器和安全转换表基地址寄存器，以指示存储非安全或安全域存储器映射数据的存储器区域定义如何将虚拟地址转换为非安全或安全域中的物理地址。

38. 发明授权

US07117284B2 Vectored interrupt control within a system having a secure domain and a non-secure domain 有权
标题翻译：具有安全域和非安全域的系统内的向量中断控制
公开(公告)号：US07117284B2
公开(公告)日：2006-10-03
申请号：US10714562
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Jonathan Sean Callan
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Jonathan Sean Callan
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.
摘要翻译：数据处理装置可以以多种模式操作，也可以在安全域或非安全域中操作。当在安全域内以安全模式操作时，程序可以访问当处理器以非安全模式操作时无法访问的安全数据。提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。向量中断控制器是可编程的，参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序，如果在适当的域中发生异常，则使用异常处理程序地址。向量中断控制器还包括指定域切换异常处理程序地址的参数，以便在处理器不在适当域中时发生异常情况时使用。

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