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31. 发明申请

US20090172048A1 MEMORY STORAGE OF FILE FRAGMENTS 审中-公开
标题翻译：文件片段的存储
公开(公告)号：US20090172048A1
公开(公告)日：2009-07-02
申请号：US11968033
申请日：2007-12-31
申请人： R. Scott Tetrick , Glenn Hinton , Dale Juenemann
发明人： R. Scott Tetrick , Glenn Hinton , Dale Juenemann
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0676
摘要： In some embodiments a beginning portion of a disk drive file fragment is stored in a memory, and the beginning portion of the disk drive file fragment is accessed from the memory. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，磁盘驱动器文件片段的开始部分存储在存储器中，并且从存储器访问磁盘驱动器文件片段的开始部分。描述和要求保护其他实施例。

32. 发明申请

US20090049446A1 PROVIDING QUALITY OF SERVICE VIA THREAD PRIORITY IN A HYPER-THREADED MICROPROCESSOR 有权
标题翻译：在超级螺旋式微处理器中通过螺纹优先提供的服务质量
公开(公告)号：US20090049446A1
公开(公告)日：2009-02-19
申请号：US11838458
申请日：2007-08-14
申请人： Matthew Merten , Santhosh Srinath , Morris Marden , John Holm , Glenn Hinton
发明人： Matthew Merten , Santhosh Srinath , Morris Marden , John Holm , Glenn Hinton
IPC分类号： G06F9/46
CPC分类号： G06F9/5011 , G06F9/3851 , G06F2209/507
摘要： A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing
摘要翻译：这里描述了一种基于优先级在多处理元件环境中提供服务质量的方法和装置。诸如保留站和流水线等资源的消耗偏向较高优先级的处理要素。在保留站中，设置掩码元素以提供对较高优先级处理元素的访问以获得更多的预留条目。在流水线中，偏置逻辑提供用于选择高优先级处理的偏好比率

33. 发明申请

US20070028048A1 Early data return indication mechanism 有权
标题翻译：早期数据返回指示机制
公开(公告)号：US20070028048A1
公开(公告)日：2007-02-01
申请号：US11541289
申请日：2006-09-28
申请人： Belliappa Kuttanna , Robert Milstrey , Stanley Domen , Glenn Hinton
发明人： Belliappa Kuttanna , Robert Milstrey , Stanley Domen , Glenn Hinton
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F12/0859
摘要： One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.
摘要翻译：公开了一种方法的一个实施例。该方法产生等待数据加载到包括第一级高速缓存（FLC）的数据高速缓存中的请求。该方法还从指令源接收请求，调度请求，然后将请求传递给具有数据高速缓存的执行单元。此外，该方法检查数据高速缓存的内容，如果数据不位于数据高速缓存中，则重播请求，并存储重放安全的请求。该方法还在数据准备好发送到处理器之前进一步检测总线时钟数据的准备状态，并将早期的数据就绪指示发送给处理器以从资源调度器中排出请求。

34. 发明授权

US07111153B2 Early data return indication mechanism 失效
标题翻译：早期数据返回指示机制
公开(公告)号：US07111153B2
公开(公告)日：2006-09-19
申请号：US10676446
申请日：2003-09-30
申请人： Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
发明人： Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/383 , G06F12/0859
摘要： A method, apparatus, and system are provided for early data return indication mechanism. According to one embodiment, data cache is accessed for data in response to a request for the data, the request received from an instruction source, and the request waits for the data to be retrieved from memory if the data is not located in the data cache, and an early data ready indication is received at a resource scheduler, the early data ready indication being received prior to receiving a data ready indication referring to the data being ready to be retrieved from the memory.
摘要翻译：提供了早期数据返回指示机制的方法，装置和系统。根据一个实施例，响应于对数据的请求，从指令源接收到的请求，数据高速缓存被访问，并且如果数据不位于数据高速缓存中，则请求等待从存储器检索数据并且在资源调度器处接收到早期数据就绪指示，在接收到准备好从存储器检索的数据的数据就绪指示之前接收到早期数据就绪指示。

35. 发明授权

US5680565A Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions 失效
标题翻译：用于在能够处理推测性指令的微处理器中执行页表行进的方法和装置
公开(公告)号：US5680565A
公开(公告)日：1997-10-21
申请号：US176363
申请日：1993-12-30
申请人： Andy Glew , Glenn Hinton , Haitham Akkary
发明人： Andy Glew , Glenn Hinton , Haitham Akkary
IPC分类号： G06F9/38 , G06F12/10 , G06F12/12
CPC分类号： G06F9/3834 , G06F12/1027 , G06F9/3842 , G06F2212/206 , G06F2212/684
摘要： A page table walk is performed in response to a data translation lookaside buffer miss based on a speculative memory instruction. In the event of a data translation lookaside buffer miss, a page miss handler determines whether the memory micro-instruction causing the miss is a speculative or non-speculative micro-instruction. If non-speculative, the page miss handler performs a non-speculative page table walk. If the memory micro-instruction causing the miss is a speculative micro-instruction, the page miss handler initiates a speculative page table walk. While performing the speculative page table walk, the page miss handler determines whether page table memory accessed during the page table walk is speculateable or non-speculateable memory. If non-speculateable, the speculative page table walk is aborted. A micro-instruction assisted page table walk is performed whenever access or dirty bits must be set for the pages accessed in the page table walk.
摘要翻译：响应于基于推测性存储器指令的数据转换后备缓存器未命中来执行页表步行。在数据转换后备缓存器未命中的情况下，页面未命中处理器确定导致未命中的存储器微指令是否是推测性或非推测性微指令。如果不推测，则页面错误处理程序执行非推测性页面表。如果导致错过的存储器微指令是推测性微指令，则页错误处理程序启动推测页表行走。在执行推测页表行进时，页面未命中处理程序确定在页表行走期间访问的页表存储器是否是可推测的或不可推测的存储器。如果不可推测，则推测页表的步行中止。无论访问页面还是脏位都必须设置为在页面表中访问的页面，执行微指令辅助页面表。

36. 发明授权

US08838935B2 Apparatus, method, and system for implementing micro page tables 有权
标题翻译：用于实现微页表的装置，方法和系统
公开(公告)号：US08838935B2
公开(公告)日：2014-09-16
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/00 , G06F12/10 , G06F12/02
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
摘要翻译：在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

37. 发明授权

US08095932B2 Providing quality of service via thread priority in a hyper-threaded microprocessor 有权
标题翻译：在超线程微处理器中通过线程优先级提供服务质量
公开(公告)号：US08095932B2
公开(公告)日：2012-01-10
申请号：US11838458
申请日：2007-08-14
申请人： Matthew Merten , Santhosh Srinath , Morris Marden , John Holm , Glenn Hinton
发明人： Matthew Merten , Santhosh Srinath , Morris Marden , John Holm , Glenn Hinton
IPC分类号： G06F9/46
CPC分类号： G06F9/5011 , G06F9/3851 , G06F2209/507
摘要： A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing element for further processing in the pipeline.
摘要翻译：这里描述了一种基于优先级在多处理元件环境中提供服务质量的方法和装置。诸如保留站和流水线等资源的消耗偏向较高优先级的处理要素。在保留站中，设置掩码元素以提供对较高优先级处理元素的访问以获得更多的预留条目。在流水线中，偏置逻辑提供了用于选择高优先级处理元件的偏好比，用于在管线中的进一步处理。

38. 发明授权

US07567471B2 High speed fanned out system architecture and input/output circuits for non-volatile memory 有权
标题翻译：高速扇出系统架构和非易失性存储器的输入/输出电路
公开(公告)号：US07567471B2
公开(公告)日：2009-07-28
申请号：US11645043
申请日：2006-12-21
申请人： Sean S. Eilert , Rodney R. Rozman , Shekoufeh Qawami , Glenn Hinton
发明人： Sean S. Eilert , Rodney R. Rozman , Shekoufeh Qawami , Glenn Hinton
IPC分类号： G11C7/00
CPC分类号： G06F13/4239 , G11C16/10 , G11C16/26 , G11C2216/14
摘要： In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.
摘要翻译：在各种实施例中，诸如NAND闪存器件的多个非易失性存储器件可以以扇形输出配置连接到主机控制器设备，其允许多个存储器件中的每一个执行读取和/或写入操作同时。每个非易失性存储器件可以包括高速输入电路和高速输出电路，使得到存储器和从存储器的传送不受闪存读/写接口的速度的限制。

39. 发明申请

US20090043965A1 EARLY DATA RETURN INDICATION MECHANISM 审中-公开
标题翻译：早期数据返回指示机制
公开(公告)号：US20090043965A1
公开(公告)日：2009-02-12
申请号：US12249623
申请日：2008-10-10
申请人： BELLIAPPA KUTTANNA , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
发明人： BELLIAPPA KUTTANNA , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
IPC分类号： G06F12/08
CPC分类号： G06F9/383 , G06F12/0859
摘要： One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.
摘要翻译：公开了一种方法的一个实施例。该方法产生等待数据加载到包括第一级高速缓存（FLC）的数据高速缓存中的请求。该方法还从指令源接收请求，调度请求，然后将请求传递给具有数据高速缓存的执行单元。此外，该方法检查数据高速缓存的内容，如果数据不位于数据高速缓存中，则重播请求，并存储重放安全的请求。该方法还在数据准备好发送到处理器之前进一步检测总线时钟数据的准备状态，并将早期的数据就绪指示发送给处理器以从资源调度器中排出请求。

40. 发明授权

US07451295B2 Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues 有权
标题翻译：数据缓存的早期数据返回指示机制，通过调度，重新安排和重播请求队列中的请求，通过早期数据就绪指示来检测数据的准备
公开(公告)号：US07451295B2
公开(公告)日：2008-11-11
申请号：US11541289
申请日：2006-09-28
申请人： Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
发明人： Belliappa Kuttanna , Robert G. Milstrey , Stanley J. Domen , Glenn Hinton
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F9/383 , G06F12/0859
摘要： One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.
摘要翻译：公开了一种方法的一个实施例。该方法产生等待数据加载到包括第一级高速缓存（FLC）的数据高速缓存中的请求。该方法还从指令源接收请求，调度请求，然后将请求传递给具有数据高速缓存的执行单元。此外，该方法检查数据高速缓存的内容，如果数据不位于数据高速缓存中，则重播请求，并存储重放安全的请求。该方法还在数据准备好发送到处理器之前进一步检测总线时钟数据的准备状态，并将早期的数据就绪指示发送给处理器以从资源调度器中排出请求。

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