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    • 36. 发明授权
    • Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency
    • 用于产生n位输出指针的电路装置,半导体存储器和用于调整读延迟的方法
    • US07428184B2
    • 2008-09-23
    • US11593234
    • 2006-11-06
    • Stefan Dietrich
    • Stefan Dietrich
    • G11C8/00
    • G11C7/22G06F5/10G11C7/222
    • A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer. The reference signal comprises an information regarding a read latency to be adjusted utilizing the output pointer, the at least one counter provides an m-bit counter reading signal comprising a current counter reading, and the decoder arrangement comprises a plurality of decoder devices each comparing the current counter reading signal with a reference value which is associated with a respective of the decoder devices. Each decoder device provides one bit of the output pointer on the basis of the comparing.
    • 用于在半导体存储器中产生n位输出指针的电路装置包括至少一个用于接受m位参考信号的m位接口,至少一个m位二进制计数器,连接在二进制计数器下游的解码器装置 ,以及用于提供输出指针的位的输出。 所述参考信号包括关于使用所述输出指针进行调整的读等待时间的信息,所述至少一个计数器提供包括当前计数器读数的m位计数器读取信号,并且所述解码器装置包括多个解码器装置, 具有与各个解码器装置相关联的参考值的当前计数器读取信号。 每个解码器装置在比较的基础上提供一位输出指针。
    • 38. 发明授权
    • Circuit for data bit inversion
    • 数据位反转电路
    • US07405981B2
    • 2008-07-29
    • US11372738
    • 2006-03-10
    • Stefan Dietrich
    • Stefan Dietrich
    • G11C7/10
    • G06F11/08G11C7/1006
    • An electric circuit for inverting a data bit of a data burst read out from a memory module comprises a buffer for buffering a data burst being comprised of at least two data words, a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously two neighbouring data words of the data words buffered in the buffer and generating an inversion flag, if the number of different data bits of the two neighbouring data words exceeds half the number of data bits of a data word, a correction device for generating a corrected inversion flag for a specific decoder of the decoders by inverting or not inverting the inversion flag of the specific decoder dependent on the inversion flag generated by the specific decoder and the inversion flags generated by the remaining of the decoders, and an inversion device comprised of a plurality of inverters, each inverting or not inverting a present of the data words of an associated of the decoders dependent on the corrected inversion flag of the associated decoder.
    • 用于反相从存储器模块读出的数据脉冲串的数据位的电路包括用于缓冲由至少两个数据字组成的数据脉冲串的缓冲器,由至少两个并联连接的解码器组成的解码器装置,每个比较 如果两个相邻数据字的不同数据位的数量超过数据字的数据位的数量的一半,则缓冲器中缓冲的数据字的两个相邻的数据字并且产生反转标志,校正装置 通过根据由特定解码器产生的反转标志和由剩余的解码器产生的反转标志反转或不反转特定解码器的反转标志来产生解码器的特定解码器的校正反转标志,以及反转装置 由多个反相器组成,每个逆变器反相或不反转依赖于解码器的相关联的数据字的存在 相关解码器的校正反转标志。