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31. 发明授权

US07906395B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07906395B2
公开(公告)日：2011-03-15
申请号：US12891481
申请日：2010-09-27
申请人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分地蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

32. 发明授权

US07867899B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US07867899B2
公开(公告)日：2011-01-11
申请号：US12111886
申请日：2008-04-29
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/44 , H01L21/02
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

33. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

34. 发明申请

US20080083946A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 有权
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译：提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

35. 发明申请

US20080023750A1 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 有权
标题翻译：具有多层氮化物层的存储单元系统
公开(公告)号：US20080023750A1
公开(公告)日：2008-01-31
申请号：US11461428
申请日：2006-07-31
申请人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译：提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层并且在顶部阻挡中间层上形成接触层。

36. 发明授权

US09412598B2 Edge rounded field effect transistors and methods of manufacturing 有权
标题翻译：边缘圆形场效应晶体管和制造方法
公开(公告)号：US09412598B2
公开(公告)日：2016-08-09
申请号：US12973756
申请日：2010-12-20
申请人： Shenqing Fang , Tung-Sheng Chen
发明人： Shenqing Fang , Tung-Sheng Chen
IPC分类号： H01L21/336 , H01L21/3105 , H01L21/321 , H01L29/792 , H01L21/28 , H01L27/115 , H01L29/51
CPC分类号： H01L21/28282 , H01L21/28202 , H01L27/11568 , H01L29/518
摘要： Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.
摘要翻译：本技术的实施例针对场效应晶体管的栅极侧壁工程。这些技术包括形成阻挡电介质区域和其表面的氮化。在阻挡电介质区域的氮化之后，在其上形成栅极区域，并且栅极区域的侧壁被氧化以围绕栅极尖锐拐角并减小栅极拐角处的电场。

37. 发明授权

US08461053B2 Self-aligned NAND flash select-gate wordlines for spacer double patterning 有权
标题翻译：自对准NAND闪存选择栅字线用于间隔双重图案化
公开(公告)号：US08461053B2
公开(公告)日：2013-06-11
申请号：US12971818
申请日：2010-12-17
申请人： Tung-Sheng Chen , Shenqing Fang
发明人： Tung-Sheng Chen , Shenqing Fang
IPC分类号： H01L21/302
CPC分类号： H01L21/302 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
摘要翻译：公开了一种用于双重图案化的方法。在一个实施例中，通过在光致抗蚀剂图案的边缘周围放置间隔图案来开始在多个核心字线的任一侧上形成一对选择栅极字线。将光致抗蚀剂图案剥离留下间隔图案。修剪掩模放置在间隔图案的一部分上。间隔图案的部分被蚀刻掉，不被修剪掩模覆盖。去除修剪掩模，其中间隔图案的第一剩余部分限定多个核心字线。放置焊盘掩模，使得焊盘掩模和间隔物图案的第二剩余部分在多个核心字线的任一侧上限定选择栅极字线。最后，通过使用激光掩模和间隔物图案的第一和第二剩余部分来蚀刻至少一个图案转印层，以将选择栅极字线和多个核心字线蚀刻成多晶硅层。

38. 发明授权

US08441041B2 Memory device peripheral interconnects 有权
标题翻译：存储器件外设互连
公开(公告)号：US08441041B2
公开(公告)日：2013-05-14
申请号：US12943679
申请日：2010-11-10
申请人： Shenqing Fang , Wenmei Li
发明人： Shenqing Fang , Wenmei Li
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/76816 , H01L23/485 , H01L27/1052 , H01L27/11529 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.
摘要翻译：在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。一个或多个外围通孔中的每一个延伸到相应的外围触点。外围的虚拟通孔位于外围通孔附近。

39. 发明授权

US08367537B2 Flash memory cell with a flair gate 有权
标题翻译：闪存单元，带有风格门
公开(公告)号：US08367537B2
公开(公告)日：2013-02-05
申请号：US11801823
申请日：2007-05-10
申请人： Meng Ding , YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
发明人： Meng Ding , YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
IPC分类号： H01L21/283
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L21/762 , H01L21/76224 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.
摘要翻译：本发明的实施例涉及一种形成存储单元的方法。该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。该方法还包括在衬底的有源区上方和STI区上形成栅极结构。栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

40. 发明授权

US08208296B2 Apparatus and method for extended nitride layer in a flash memory 有权
标题翻译：闪存中的延伸氮化物层的装置和方法
公开(公告)号：US08208296B2
公开(公告)日：2012-06-26
申请号：US12706710
申请日：2010-02-16
申请人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
发明人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/66833
摘要： A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.
摘要翻译：提供了一种用于存储信息的方法和装置。存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层延伸到至少一个浅沟槽中。

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