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31. 发明授权

US5943682A Programmable control sequencer of disk controller and method for map allocation therefor 失效
标题翻译：磁盘控制器的可编程控制定序器及其分配方法
公开(公告)号：US5943682A
公开(公告)日：1999-08-24
申请号：US777142
申请日：1996-12-30
申请人： Chan-Geu Park , Jung-Il Park , Yong-Woo Park , Jun-Jin Kong
发明人： Chan-Geu Park , Jung-Il Park , Yong-Woo Park , Jun-Jin Kong
IPC分类号： G06F13/00 , G06F3/06 , G11B20/12 , G11B20/18 , G11B27/10 , G11B27/11 , G11B27/30
CPC分类号： G06F3/0601 , G11B20/1258 , G11B27/105 , G11B27/11 , G11B27/3027 , G06F2003/0692 , G11B20/1833 , G11B2220/20 , G11B2220/65
摘要： An improved programmable control sequencer and a method for its map allocation capable of reducing the size of program RAM used in a disk controller of a magnetic disk drive storage system, thereby efficiently reducing a work load of a microcontroller unit in the disk controller. The map allocation method is performed in a program random access memory having a 32.times.2 byte size of data storage area in the disk controller, the program random access memory being provided with the sequencer map allocation including a branch field, a next address/count field, an output field, a gate field, a field region and a data selection field. The branch field is provided with branch condition or count field enable information. The next address/count field selectively has a next address or a count value according to the branch condition. The output field is usable for testing synchronization outside the programmable control sequencer and the gate field for performing Read/Write gate control and making increase of target sector number and decrease of disk sector transmit count. The field region represents ECC/CRC block and CDR return and the data selection field is usable for comparing data from any data register with data read of the disk, thereby processing the data according to the compared result.
摘要翻译：一种改进的可编程控制定序器及其映射分配方法，其能够减小磁盘驱动器存储系统的磁盘控制器中使用的程序RAM的大小，从而有效地降低了磁盘控制器中的微控制器单元的工作负载。地图分配方法在盘控制器中具有数据存储区域的32×2字节大小的程序随机存取存储器中执行，程序随机存取存储器被提供有定序器映射分配，包括分支字段，下一个地址/计数字段，输出字段，门字段，字段区域和数据选择字段。分支域具有分支条件或计数字段使能信息。下一个地址/计数字段根据分支条件选择性地具有下一个地址或计数值。输出字段可用于测试可编程控制定序器外的同步和用于执行读/写门控制的栅极场，并增加目标扇区号和减少磁盘扇区传输计数。场区域表示ECC / CRC块和CDR返回，并且数据选择字段可用于将来自任何数据寄存器的数据与盘的数据读取进行比较，从而根据比较结果处理数据。

32. 发明授权

US10007572B2 Memory system and method of operating the memory system 有权
公开(公告)号：US10007572B2
公开(公告)日：2018-06-26
申请号：US15001012
申请日：2016-01-19
申请人： Dong-Min Shin , Jun-Jin Kong , Beom-Kyu Shin , Eun-Chu Oh , Pil-Sang Yoon
发明人： Dong-Min Shin , Jun-Jin Kong , Beom-Kyu Shin , Eun-Chu Oh , Pil-Sang Yoon
IPC分类号： G06F11/08 , H03M13/11 , G06F11/10 , H03M13/25 , H03M13/00
CPC分类号： G06F11/085 , G06F11/1012 , G06F11/1048 , H03M13/00 , H03M13/036 , H03M13/09 , H03M13/1102 , H03M13/1162 , H03M13/1165 , H03M13/1174 , H03M13/118 , H03M13/1182 , H03M13/1515 , H03M13/19 , H03M13/255 , H03M13/2912
摘要： A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

33. 发明申请

US20130060985A1 DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY 有权
标题翻译：能够采用外部存储器的设备
公开(公告)号：US20130060985A1
公开(公告)日：2013-03-07
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/16
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

34. 发明授权

US07450667B2 Apparatus and method for decoding data of unknown frame length 失效
标题翻译：用于解码未知帧长度的数据的装置和方法
公开(公告)号：US07450667B2
公开(公告)日：2008-11-11
申请号：US09897732
申请日：2001-07-03
申请人： Jae-Hong Kim , Jun-Jin Kong , Sung-Han Choi
发明人： Jae-Hong Kim , Jun-Jin Kong , Sung-Han Choi
IPC分类号： H03D1/00 , H03M13/03
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4169
摘要： An apparatus decodes data of unknown frame length. The decoding apparatus includes a preliminary decoding part and a decoded data outputting part. The preliminary decoding part decodes data into preliminarily decoded data according to each of the possible frame lengths. The decoded data outputting part selectively outputs data among the preliminary decoding data that correspond to a detected frame length. Accordingly, memory can be efficiently utilized, and decoding efficiency deterioration is prevented.
摘要翻译：装置解码未知帧长度的数据。解码装置包括初步解码部分和解码数据输出部分。初步解码部分根据每个可能的帧长度将数据解码为预先解码的数据。解码数据输出部分选择性地输出与检测到的帧长度对应的初步解码数据中的数据。因此，可以有效地利用存储器，并且防止解码效率劣化。

35. 发明授权

US06674807B1 Communication apparatus and method for a CDMA communication system 有权
标题翻译： CDMA通信系统的通信装置和方法
公开(公告)号：US06674807B1
公开(公告)日：2004-01-06
申请号：US09489235
申请日：2000-01-21
申请人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
发明人： Chang-Soo Park , Jun-Jin Kong , Hee-Won Kang , Jae-Yoel Kim , Jong-Seon No , Kyeong-Cheol Yang
IPC分类号： H04L2302
CPC分类号： H04L1/0059 , H03M13/09 , H03M13/23 , H03M13/27 , H03M13/356 , H03M13/37 , H03M13/6356 , H03M13/6362 , H04L1/0041
摘要： A communication device for a direct sequence code division multiple access (DS-CDMA) communication system is disclosed. The communication device comprises a CRC (Cyclic Redundancy Code) generator for generating CRC bits according to input data bits and adding the generated CRC bits to the input data bits; a channel encoder for encoding the CRC-added data bits using a coding rate R=1/6 convolutional code of a generator polynomial of (457, 755, 551, 637, 625, 727); and an interleaver for interleaving the coded data bits.
摘要翻译：公开了一种用于直接序列码分多址（DS-CDMA）通信系统的通信设备。通信设备包括CRC（循环冗余码）发生器，用于根据输入数据位产生CRC比特，并将所生成的CRC比特加到输入数据比特; 使用（457,755,551,637,675,727）的生成多项式的编码率R = 1/6卷积码对CRC相加数据比特进行编码的信道编码器; 以及用于交织编码数据位的交织器。

36. 发明授权

US5987631A Apparatus for measuring bit error ratio using a viterbi decoder 失效
标题翻译：使用维特比解码器测量误码率的装置
公开(公告)号：US5987631A
公开(公告)日：1999-11-16
申请号：US944647
申请日：1997-10-06
申请人： Jun-Jin Kong
发明人： Jun-Jin Kong
IPC分类号： H03M13/00 , H03M13/23 , H03M13/41 , H03M13/45 , H04L1/00 , H04L1/20 , H04W24/00 , G06F11/00
CPC分类号： H04L1/203 , H03M13/41 , H03M13/45 , H04L1/0054 , H04L1/0059 , H04L1/0061 , H04L1/208
摘要： An apparatus for accurately measuring a bit error ratio by using a viterbi decoder to improve the performance of a communication system that uses cyclic redundancy codes and trellis codes to detect and correct errors. The apparatus generates new cyclic redundancy codes and substitutes them in place of the transmitted cyclic redundancy codes by using decoded data that has been processed by a viterbi decoder. The apparatus then regenerates trellis encoded data by using reconstructed data that contains the new cyclic redundancy codes. Finally, the re-encoded data are compared with the transmitted data to calculate a bit error ratio. The apparatus consists of a viterbi decoding unit, a cyclic redundancy code regeneration unit, a cyclic redundancy code selecting unit, a cyclic redundancy code generating unit, a trellis re-encoding unit, a time delaying unit, a data comparing unit and a bit error ratio measuring unit.
摘要翻译：一种用于通过使用维特比解码器来精确地测量误码率的装置，以改善使用循环冗余码和网格码来检测和校正错误的通信系统的性能。该设备通过使用由维特比解码器处理的解码数据，生成新的循环冗余码并代替发送的循环冗余码。然后，该装置通过使用包含新的循环冗余码的重构数据来再生网格编码数据。最后，将重新编码的数据与发送的数据进行比较，以计算误比特率。该装置由维特比解码单元，循环冗余码再生单元，循环冗余码选择单元，循环冗余码生成单元，网格重编码单元，时间延迟单元，数据比较单元和位错误比率测量单元。

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