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31. 发明申请

US20110102020A1 BALANCED PHASE DETECTOR 有权
标题翻译：平衡相检测器
公开(公告)号：US20110102020A1
公开(公告)日：2011-05-05
申请号：US12939869
申请日：2010-11-04
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G01R25/00
CPC分类号： H03D13/004
摘要： Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.
摘要翻译：公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。一个或多个实施例的相位检测电路包括交叉耦合锁存器，其配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

32. 发明授权

US07622970B2 Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency 有权
标题翻译：用于控制延迟或锁相环作为环路频率的函数的装置和方法
公开(公告)号：US07622970B2
公开(公告)日：2009-11-24
申请号：US12046652
申请日：2008-03-12
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H03L7/0891 , H03L7/10
摘要： A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.
摘要翻译：公开了用于延迟锁定环（DLL）或锁相环（PLL）的方法和电路，其改善了高频下的环路稳定性，并允许最大跟踪带宽，而不管过程，电压或温度变化。该技术的核心是以更接近其自身固有带宽（1 / tLoop）的较低频率有效地操作环路，而不是在时钟信号（1 / tCK）的较高频率处。为了做到这一点，在一个实施例中，在循环操作之前测量或估计环路延迟t L oop。然后，相位检测器使能接近环路频率1 / tLoop。简而言之，使相位检测器在无用的延迟时间期间看不到活动，从而防止环路过度反应并变得不稳定。

33. 发明申请

US20090072860A1 OFF-CHIP DRIVER APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：离散驱动器装置，系统和方法
公开(公告)号：US20090072860A1
公开(公告)日：2009-03-19
申请号：US11854973
申请日：2007-09-13
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/01721 , H03K19/0005
摘要： Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit.
摘要翻译：装置，方法和系统包括具有与片外驱动器并联耦合的输出驱动器的片外驱动器，以在一段时间内提供初始驱动强调。输出驱动器可以包括耦合到片外驱动器的输出的第一晶体管和第二晶体管，以在两个晶体管在初始时间段通电时提供附加的初始驱动强度强度。该时间段可以由反相延迟电路设置。

34. 发明申请

US20060232315A1 Variable delay line with multiple hierarchy 有权
标题翻译：具有多层次的可变延迟线
公开(公告)号：US20060232315A1
公开(公告)日：2006-10-19
申请号：US11107587
申请日：2005-04-15
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked loop (DLL). In one embodiment, a coarse unit delay provides a delayed representation of an input clock. The original and delayed versions of the input clock are presented to a phase mixer block, which is controllable to weight its output to a phase between one of the two input clock signals. The output of the phase mixer block is then provided to a controllable variable delay line capable of adding further coarse delay into the processed signal. To assist in boundary switching, multiplexers are provided in the path between the original and delayed versions of the input clock and the phase mixer block, which provides the ability to boundary shift without having to reset the phase mixer.
摘要翻译：本文公开了改进的分层延迟线（HDL）的简化设计。 HDL可以在输入时钟信号和输出时钟信号之间提供精确的相位控制，并且具有延迟锁定环（DLL）中的可变延迟的特殊用途。在一个实施例中，粗略单位延迟提供输入时钟的延迟表示。输入时钟的原始和延迟版本被呈现给相位混频器模块，该相位混频器模块可控制以将其输出加权到两个输入时钟信号之一之间的相位。然后将相位混合器块的输出提供给能够将进一步的粗延迟加入到处理的信号中的可控可变延迟线。为了协助边界切换，多路复用器被提供在输入时钟的原始和延迟版本与相位混合器块之间的路径中，这提供了边界移位的能力，而不必复位相位混频器。

35. 发明申请

US20050285643A1 Digital frequency-multiplying DLLs 有权
公开(公告)号：US20050285643A1
公开(公告)日：2005-12-29
申请号：US11195154
申请日：2005-08-01
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03L7/06 , H03L7/089 , H03L7/099 , H03L7/18
CPC分类号： H03L7/18 , H03L7/089 , H03L7/0997 , H03L7/0998
摘要： Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.

36. 发明申请

US20050248377A1 Clock capture in clock synchronization circuitry 有权
标题翻译：时钟同步电路中的时钟捕捉
公开(公告)号：US20050248377A1
公开(公告)日：2005-11-10
申请号：US10840015
申请日：2004-05-05
申请人： Adrian Drexler , Debra Bell , Tyler Gomm , Seong-Hoon Lee
发明人： Adrian Drexler , Debra Bell , Tyler Gomm , Seong-Hoon Lee
IPC分类号： G11C7/22 , H03L7/08 , H03L7/081 , H03L7/06
CPC分类号： H03L7/08 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.
摘要翻译：时钟捕获同步电路首先从参考时钟信号产生同步的时钟信号，然后捕获同步的时钟信号，并在参考时钟信号被去除之后继续输出同步的时钟信号。时钟捕获同步电路还减少同步时钟信号中的输入参考抖动。

37. 发明申请

US20050127965A1 Generating multi-phase clock signals using hierarchical delays 失效
标题翻译：使用分层延迟生成多相时钟信号
公开(公告)号：US20050127965A1
公开(公告)日：2005-06-16
申请号：US10734506
申请日：2003-12-12
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G11C7/22 , H03K5/00 , H03K5/13 , H03K5/15 , H03L7/06 , H03L7/081
CPC分类号： H03L7/0814 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/15013 , H03K2005/00286 , H03L7/0818
摘要： Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.
摘要翻译：提供了使用数字控制分级延迟单元（HD）产生多相时钟信号的电路和方法。多个串行耦合的HD输出相对于参考时钟信号相移的时钟信号。每个HD包括提供相关输入信号的粗略相位调整的一个或两个可变延迟线。每个HD还包括提供输入信号的精细相位调整的一个或多个相位混合器。

38. 发明授权

US06853226B2 Register controlled delay locked loop having an acceleration mode 有权
标题翻译：具有加速模式的寄存器控制延迟锁定环
公开(公告)号：US06853226B2
公开(公告)日：2005-02-08
申请号：US10619353
申请日：2003-07-14
申请人： Jong-Tae Kwak , Seong-Hoon Lee
发明人： Jong-Tae Kwak , Seong-Hoon Lee
IPC分类号： G06F1/12 , G11C11/407 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/081 , H03L7/087 , H03L7/107 , H03L7/06
CPC分类号： H03L7/0805 , H03L7/0814 , H03L7/087 , H03L7/107
摘要： A register controlled delay locked loop having an acceleration mode corresponding to an increase of the operation speed of a memory device is used to improve accuracy. The register controlled delay locked loop includes a delay line, a delay model, a delay block, a first phase comparator, and a second phase comparator, a mode decision block, a shift register control block, and a shift register.
摘要翻译：使用具有对应于存储器件的操作速度的增加的加速模式的寄存器控制延迟锁定环来提高精度。寄存器控制延迟锁定环包括延迟线，延迟模型，延迟块，第一相位比较器和第二相位比较器，模式判定块，移位寄存器控制块和移位寄存器。

39. 发明授权

US06483359B2 Delay locked loop for use in semiconductor memory device 有权
标题翻译：延迟锁定环用于半导体存储器件
公开(公告)号：US06483359B2
公开(公告)日：2002-11-19
申请号：US09897829
申请日：2001-06-29
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03L706
CPC分类号： G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A delay locked loop (DLL) is disclosed which has finer adjustability. The delay locked loop generally includes: a first shift register for controlling a delay amount of an internal clock in response to a first shift-right signal and a first shift-left signal, a first delay line for delaying the internal clock according to an output of the first shift register, wherein the first delay line includes a plurality of first delay units, each first delay unit having a first delay amount; a second shift register for controlling the delay amount of an output of the first delay line in response to a second shift-right signal and a second shift-left signal, which are outputted from the first shift register; and a second delay line for delaying an output of the first delay line by a predetermined delay amount in response to an output of the second shift register, wherein the second delay line includes a plurality of second delay units, each second delay unit having a second delay amount larger than the first delay amount.
摘要翻译：公开了具有更好的可调整性的延迟锁定环（DLL）。延迟锁定环通常包括：第一移位寄存器，用于响应于第一右移信号和第一左移信号来控制内部时钟的延迟量;第一延迟线，用于根据输出延迟内部时钟所述第一延迟线包括多个第一延迟单元，每个第一延迟单元具有第一延迟量; 第二移位寄存器，用于响应于从第一移位寄存器输出的第二右移信号和第二左移信号来控制第一延迟线的输出的延迟量; 以及第二延迟线，用于响应于所述第二移位寄存器的输出而延迟所述第一延迟线的输出预定延迟量，其中所述第二延迟线包括多个第二延迟单元，每个第二延迟单元具有第二延迟线延迟量大于第一延迟量。

40. 发明授权

US06437618B1 Delay locked loop incorporating a ring type delay and counting elements 有权
公开(公告)号：US06437618B1
公开(公告)日：2002-08-20
申请号：US09888905
申请日：2001-06-25
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03L706
摘要： Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input unit for receiving an external clock signal from which a clock input signal is created; a delay monitor for receiving a clock output signal to monitor a time delay introduced on the clock input signal; and a phase detection unit for receiving the clock input signal and an output of the delay monitor for determining a difference in phase between the clock input and output signals to produce a shift control signal. A shift register for controlling the adjustment of the time delay and a delay line for adjusting the time delay are also provided in the delay locked loop. Both the shift register and the delay line have a ring configuration on their outputs. The delay locked loop provided also includes a first and a second counter for counting the number of data signals outputted from the delay line and the shift register, respectively; a comparator for comparing these counted numbers; and an output unit for receiving the output of the delay line and the compared value to produce the clock output signal.

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