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    • 35. 发明申请
    • Liquid crystal display panel and method of fabricating thereof
    • 液晶显示面板及其制造方法
    • US20060262265A1
    • 2006-11-23
    • US11304534
    • 2005-12-16
    • Min Lee
    • Min Lee
    • G02F1/1339
    • G02F1/13394G02F1/1339G02F2001/133388
    • A liquid crystal display panel and a fabricating method thereof for preventing a generation of stains caused by a cell gap difference between an active area and an outside area are disclosed. In the liquid crystal display panel, an adhesive is placed between an upper substrate and a lower substrate that are closed in such a manner as to join an upper substrate from a lower substrate. A liquid crystal layer is provided at a closed area defined by the adhesive by a dropping system. A first pattern spacer is positioned at an active area between the upper substrate and the lower substrate. A second pattern spacer is provided such that an outside area thereof enclosing said active area has a different arrangement density from the first pattern spacer and is provided at the same plane as the first pattern spacer.
    • 公开了一种液晶显示面板及其制造方法,用于防止由有源区域和外部区域之间的单元间隙差引起的污渍的产生。 在液晶显示面板中,粘合剂被放置在上基板和下基板之间,以从下基板接合上基板的方式封闭。 在由粘合剂由滴落系统限定的封闭区域处设置液晶层。 第一图案间隔物位于上基板和下基板之间的有源区域。 提供第二图案间隔件,使得封闭所述有源区域的外部区域具有与第一图案间隔物不同的排列密度,并且设置在与第一图案间隔物相同的平面处。
    • 36. 发明申请
    • Gate structure of semiconductor device and method for forming the same
    • 半导体器件的栅极结构及其形成方法
    • US20060151839A1
    • 2006-07-13
    • US11268846
    • 2005-11-08
    • Young KimJun ChangMin LeeYong Eun
    • Young KimJun ChangMin LeeYong Eun
    • H01L29/78H01L21/4763
    • H01L27/10876H01L21/2815H01L29/66636
    • Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
    • 本文公开了一种用于形成半导体器件的栅极结构的方法。 该方法包括形成多个栅极,其包括依次层叠在具有场氧化膜的硅基板上的第一栅极电介质膜,第一栅极导电膜和栅极硅化物膜,在第一栅极的一侧形成热氧化膜 将暴露在所述多个栅极之间的硅衬底蚀刻到预定深度以形成多个沟槽,在所述沟槽的内壁上形成第二栅极氧化膜,并且形成间隔物形状的第二栅极导电膜 第二栅极氧化膜的预定区域,以及第一栅极导电膜,栅极硅化物膜和热氧化物膜的一侧。
    • 37. 发明申请
    • Method for manufacturing a cell transistor of a semiconductor memory device
    • 半导体存储器件的单元晶体管的制造方法
    • US20060141716A1
    • 2006-06-29
    • US11150026
    • 2005-06-10
    • Kyoung-Bong RouhSeung JinMin Lee
    • Kyoung-Bong RouhSeung JinMin Lee
    • H01L21/336
    • H01L29/66575H01L27/10873H01L29/66492
    • Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor substrate; performing a first thermal annealing on the semiconductor substrate where the threshold voltage adjust region is formed; forming a gate insulating film and gate electrodes on top of the semiconductor substrate between the device isolation films; forming a halo ion implantation region by ion-implanting a first conductive impurity dopant into the semiconductor substrate corresponding to a drain region exposed by the gate electrodes; performing a second thermal annealing on the semiconductor substrate where the halo ion implantation region is formed; and forming source/drain regions by ion-implanting a second conductive impurity dopant into the semiconductor substrate exposed by the gate electrodes. This method can reduce the turn-off leakage current of the cell transistor since the dopant dose of the threshold voltage adjust region can be reduced while maintaining the threshold voltage by increasing the dopant diffusion of the threshold voltage adjust region.
    • 公开了半导体存储器件的单元晶体管的制造方法。 该方法包括以下步骤:在半导体衬底上形成器件隔离膜和阱; 通过将第一导电杂质掺杂剂离子注入到所述半导体衬底的阱中来形成阈值电压调整区域; 在形成有阈值电压调整区域的半导体衬底上进行第一热退火; 在半导体衬底的顶部在器件隔离膜之间形成栅极绝缘膜和栅电极; 通过将第一导电杂质掺杂剂离子注入对应于由栅电极暴露的漏区的半导体衬底中形成晕圈离子注入区; 在形成有所述卤素离子注入区域的所述半导体衬底上进行第二热退火; 以及通过将第二导电杂质掺杂剂离子注入到由所述栅电极暴露的所述半导体衬底中来形成源/漏区。 该方法可以减小单元晶体管的截止漏电流,因为阈值电压调整区域的掺杂剂剂量可以通过增加阈值电压调整区域的掺杂剂扩散来维持阈值电压而降低。