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31. 发明授权

US5624859A Method for providing device isolation and off-state leakage current for a semiconductor device 失效
标题翻译：用于为半导体器件提供器件隔离和截止状态漏电流的方法
公开(公告)号：US5624859A
公开(公告)日：1997-04-29
申请号：US476388
申请日：1995-06-07
申请人： David K. Y. Liu , Mark T. Ramsbey
发明人： David K. Y. Liu , Mark T. Ramsbey
IPC分类号： H01L21/265 , H01L21/336 , H01L21/762
CPC分类号： H01L29/66575 , H01L21/26586 , H01L21/762
摘要： A method and system for providing a semiconductor device with device isolation and leakage current control which entails processing a semiconductor substrate to form a semiconductor circuit, and providing at least one high energy implant on the semiconductor circuit is disclosed. The high energy implant is provided at an angle to source and drain regions of the semiconductor circuit so as to allow a dosage from the at least one high energy implant below and away from the surface of the active device region. In so doing, a profile is provided in which dopant distribution is substantially uniform. Therefore, the breakdown characteristics are increased and the junction capacitance of the device is reduced. Accordingly, a device manufactured in accordance with the present invention has significant advantages over devices manufactured in accordance with conventional processes.
摘要翻译：公开了一种用于提供具有器件隔离和漏电流控制的半导体器件的方法和系统，其需要处理半导体衬底以形成半导体电路，并且在半导体电路上提供至少一个高能量注入。与半导体电路的源极和漏极区成角度地设置高能量注入，从而允许来自至少一个高能量注入的剂量低于和远离有源器件区域的表面。在这样做时，提供其中掺杂剂分布基本上均匀的轮廓。因此，击穿特性增加，并且器件的结电容减小。因此，根据本发明制造的装置与根据常规方法制造的装置相比具有显着的优点。

32. 发明授权

US09570175B2 Incrementally programmable non-volatile memory 有权
标题翻译：增量式可编程非易失性存储器
公开(公告)号：US09570175B2
公开(公告)日：2017-02-14
申请号：US14452269
申请日：2014-08-05
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： G11C16/10 , G11C16/04 , G11C16/22 , H01L27/112 , G11C17/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/14 , G11C16/22 , G11C17/12 , G11C17/18 , H01L27/11206
摘要： An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a Vt representing a particular binary logic state can be changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
摘要翻译：诸如标称OTP单元的可编程非易失性设备阵列被调整为使得表示特定二进制逻辑状态的Vt可以随着时间而改变。这允许重新编程和仿真几次或多次可编程器件。

33. 发明授权

US09324438B2 Method of operating incrementally programmable non-volatile memory 有权
标题翻译：操作增量式可编程非易失性存储器的方法
公开(公告)号：US09324438B2
公开(公告)日：2016-04-26
申请号：US14452275
申请日：2014-08-05
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： G11C16/04 , G11C16/10 , H01L27/112 , G11C16/22 , G11C17/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/14 , G11C16/22 , G11C17/12 , G11C17/18 , H01L27/11206
摘要： An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
摘要翻译：操作诸如标称OTP单元的可编程非易失性设备的阵列，使得表示特定二进制逻辑状态的Vt随时间而改变。这允许重新编程和仿真几次或多次可编程器件。

34. 发明授权

US09305931B2 Zero cost NVM cell using high voltage devices in analog process 有权
标题翻译：零成本NVM单元在模拟过程中使用高压器件
公开(公告)号：US09305931B2
公开(公告)日：2016-04-05
申请号：US13468417
申请日：2012-05-10
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： H01L21/336 , H01L29/78 , H01L29/778 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L29/7885 , H01L27/11521 , H01L27/11541 , H01L27/11558 , H01L29/1095 , H01L29/42324 , H01L29/66825 , H01L29/7816 , H01L29/7883
摘要： A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.
摘要翻译：公开了一种位于集成电路的高电压区域内的非易失性存储单元和阵列结构。电池利用基于栅极和漂移区域之间的重叠的电容耦合来施加编程电压。使用可以用于注入热电子的漏极延伸来实现编程。电池可以作为一次性可编程（OTP）或多时间可编程（MTP）器件运行。电池的制造依赖于与高电压装置相关的处理步骤，因此避免了对附加掩模，制造步骤等的需要。

35. 发明授权

US06693027B1 Method for configuring a device to include a negative differential resistance (NDR) characteristic 有权
标题翻译：用于配置设备以包括负差分电阻（NDR）特性的方法
公开(公告)号：US06693027B1
公开(公告)日：2004-02-17
申请号：US10298917
申请日：2002-11-18
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L2128
CPC分类号： H01L29/7881 , G11C5/142 , H01L29/788 , H01L29/792
摘要： A process for forming/configuring a device to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is implemented by incorporating a dynamic threshold voltage in such device. An onset point for the NDR characteristic is also adjustable during a manufacturing process to enhance the performance of an NDR device.
摘要翻译：公开了一种用于形成/配置器件以包括负差分电阻（NDR）特性的过程。在FET实施例中，通过在该装置中并入动态阈值电压来实现NDR特性。在制造过程中，NDR特性的起始点也是可调节的，以增强NDR设备的性能。

36. 发明授权

US06680245B1 Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process 有权
标题翻译：使用公共MOS工艺制造负差分电阻（NDR）器件和非NDR器件的方法
公开(公告)号：US06680245B1
公开(公告)日：2004-01-20
申请号：US10232129
申请日：2002-08-30
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L2128
CPC分类号： H01L29/7881 , G11C5/142 , H01L29/788 , H01L29/792
摘要： A semiconductor manufacturing process is disclosed that is suitable for making both negative differential resistance (NDR) and non-NDR devices at the same time. An NDR process is thus integrated within a conventional CMOS process so that compatibility with existing fabrication procedures is maintained. In addition, many of the NDR process steps and non-NDR process steps are shared in common to form features of such devices at the same time.
摘要翻译：公开了适用于同时制造负差分电阻（NDR）和非NDR器件的半导体制造工艺。因此，NDR工艺集成在常规CMOS工艺中，以便保持与现有制造工艺的兼容性。此外，许多NDR流程步骤和非NDR流程步骤共同共享，以同时形成这些设备的功能。

37. 发明授权

US5995418A Circuit and method for erasing flash memory array 失效
公开(公告)号：US5995418A
公开(公告)日：1999-11-30
申请号：US251040
申请日：1999-02-18
申请人： Kou-Su Chen , David K. Y. Liu
发明人： Kou-Su Chen , David K. Y. Liu
IPC分类号： G11C16/02 , G11C16/34 , G11C16/04
CPC分类号： G11C16/345 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C2216/18
摘要： A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

38. 发明授权

US5693972A Method and system for protecting a stacked gate edge in a semiconductor device from self-aligned source (sas) etch in a semiconductor device 失效
标题翻译：用于保护半导体器件中的堆叠栅极边缘的半导体器件中的自对准源（sas）蚀刻的方法和系统
公开(公告)号：US5693972A
公开(公告)日：1997-12-02
申请号：US769178
申请日：1996-12-18
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
摘要翻译：公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

39. 发明授权

US5534455A Method for protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch 失效
标题翻译：用于保护半导体器件中的堆叠栅极边缘与自对准源（SAS）蚀刻的方法
公开(公告)号：US5534455A
公开(公告)日：1996-07-09
申请号：US433267
申请日：1995-05-02
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
摘要翻译：公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

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