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31. 发明授权

US06544461B1 Test carrier with molded interconnect for testing semiconductor components 失效
标题翻译：带有模拟互连的测试载体，用于测试半导体元件
公开(公告)号：US06544461B1
公开(公告)日：2003-04-08
申请号：US09677555
申请日：2000-10-02
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： B29C4502
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.
摘要翻译：提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。载体包括模制塑料基底，引线框架和互连件。互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。替代实施例的载体包括多个互连件模制或层压的板。另外，夹子构件保持电路板上与组件电连通的组件。可以在模制步骤期间使用垫圈来保护互连触点。

32. 发明授权

US5952840A Apparatus for testing semiconductor wafers 失效
公开(公告)号：US5952840A
公开(公告)日：1999-09-14
申请号：US770942
申请日：1996-12-31
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

33. 发明授权

US6064216A Apparatus for testing semiconductor wafers 有权
标题翻译：半导体晶片测试装置
公开(公告)号：US6064216A
公开(公告)日：2000-05-16
申请号：US241553
申请日：1999-02-01
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
摘要翻译：提供了一种用于测试半导体晶片的方法，装置和系统。该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

34. 发明授权

US5915977A System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
标题翻译：用于与凸起的半导体部件进行临时电连接的系统和互连
公开(公告)号：US5915977A
公开(公告)日：1999-06-29
申请号：US138612
申请日：1998-08-24
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

35. 发明授权

US06553276B2 Method of using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
标题翻译：集成电路（IC）使用数据的方法已经进行了修复，以选择IC将要进行的程序，例如额外修理
公开(公告)号：US06553276B2
公开(公告)日：2003-04-22
申请号：US10071961
申请日：2002-02-05
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F1900
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：一种集成电路（IC）制造过程中的发明方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修复，包括将数据与每个的保险丝ID相关联地存储 IC的。例如，在制造过程中，IC的ID代码将自动读取，例如打开/短路测试。然后访问与IC的ID代码相关联存储的数据，并且根据访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

36. 发明授权

US5931685A Interconnect for making temporary electrical connections with bumped semiconductor components 失效
标题翻译：互连用于与凸起的半导体元件进行临时电连接
公开(公告)号：US5931685A
公开(公告)日：1999-08-03
申请号：US867551
申请日：1997-06-02
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

37. 发明授权

US5907492A Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
公开(公告)号：US5907492A
公开(公告)日：1999-05-25
申请号：US871015
申请日：1997-06-06
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F11/00 , G06F19/00
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

38. 发明授权

US07561938B2 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs 失效
标题翻译：使用有关制造程序集成电路（ICS）的数据的方法已经进行了修复，以选择IC将经历的程序，例如额外修理
公开(公告)号：US07561938B2
公开(公告)日：2009-07-14
申请号：US11545067
申请日：2006-10-06
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F19/00
CPC分类号： G03F7/7065 , G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

39. 发明授权

US07120513B1 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs 有权
标题翻译：使用有关制造程序集成电路（ICS）的数据的方法已经进行了修复，以选择ICS将要进行的程序，如额外修理
公开(公告)号：US07120513B1
公开(公告)日：2006-10-10
申请号：US09653272
申请日：2000-08-31
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F19/00
CPC分类号： G03F7/7065 , G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：一种集成电路（IC）制造过程中的发明方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修复，包括将数据与每个的保险丝ID相关联地存储 IC的。例如，在制造过程中，IC的ID代码将自动读取，例如打开/短路测试。然后访问与IC的ID代码相关联存储的数据，并且根据访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

40. 发明授权

US07049840B1 Hybrid interconnect and system for testing semiconductor dice 失效
公开(公告)号：US07049840B1
公开(公告)日：2006-05-23
申请号：US09302576
申请日：1999-04-30
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
IPC分类号： G01R31/02
CPC分类号： G01R1/0466 , G01R1/0735
摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

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