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31. 发明申请

US20050256019A1 Enzymatic ammonolysis process for the preparation of intermediates for DPP IV inhibitors 有权
标题翻译：用于制备DPP IV抑制剂中间体的酶促氨解过程
公开(公告)号：US20050256019A1
公开(公告)日：2005-11-17
申请号：US11119552
申请日：2005-05-02
申请人： Ramesh Patel , Ronald Hanson , Iqbal Gill , David Brzozowski , Paul Skonezny , Michael Politino , Jason Chen , Francisco Moris-Varas , Brenda White
发明人： Ramesh Patel , Ronald Hanson , Iqbal Gill , David Brzozowski , Paul Skonezny , Michael Politino , Jason Chen , Francisco Moris-Varas , Brenda White
IPC分类号： C07D207/22 , C07D209/52 , C07K5/065 , C11D3/00 , C12P17/10
CPC分类号： C07D207/22 , C07D209/52 , C07K5/06078 , C12P13/04 , C12P17/10 , C12P17/12
摘要： An enzymatic ammonolysis process is provided for the preparation of intermediates used in preparing dipeptidyl peptidase IV inhibitors wherein the enzyme Candida antarctica lipase-B is used to catalyze the ammonolysis process.
摘要翻译：提供酶促氨解方法用于制备用于制备二肽基肽酶IV抑制剂的中间体，其中使用南极假丝酵母脂肪酶-B来催化氨解过程。

32. 发明申请

US20050112820A1 METHOD FOR FABRICATING FLASH MEMORY DEVICE AND STRUCTURE THEREOF 审中-公开
标题翻译：用于制造闪速存储器件及其结构的方法
公开(公告)号：US20050112820A1
公开(公告)日：2005-05-26
申请号：US10711445
申请日：2004-09-20
申请人： Jason Chen , Ting-Chang Chang
发明人： Jason Chen , Ting-Chang Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423
CPC分类号： B82Y10/00 , H01L29/40114 , H01L29/42332
摘要： A method for fabricating a flash memory device is provided. A tunnel oxide layer is formed over a substrate. Thereafter, a floating gate, an inter-gate dielectric layer, and a control gate are sequentially formed over the tunnel oxide layer. Since the floating gate includes a plurality of nanocrystals, the memory cell can still normally function even if partial region of the floating gate is impaired.
摘要翻译：提供了一种制造闪速存储器件的方法。在衬底上形成隧道氧化物层。此后，在隧道氧化物层上依次形成浮栅，栅极间电介质层和控制栅极。由于浮置栅极包括多个纳米晶体，因此即使浮动栅极的部分区域受损，存储单元也能正常工作。

33. 外观设计

USD412367S Halogen bulb 失效
公开(公告)号：USD412367S
公开(公告)日：1999-07-27
申请号：US82169
申请日：1998-01-16
申请人： Jason Chen
设计人： Jason Chen

34. 发明授权

US5737257A Method and apparatus for compression of integer multiplication table 失效
标题翻译：用于整数乘法表压缩的方法和装置
公开(公告)号：US5737257A
公开(公告)日：1998-04-07
申请号：US527792
申请日：1995-09-13
申请人： Jason Chen , Paul Chen , George Chang
发明人： Jason Chen , Paul Chen , George Chang
IPC分类号： G06F1/035 , G06F7/52
CPC分类号： G06F7/53 , G06F1/0356
摘要： A method of compressing an integer multiplication table including the steps of first eliminating one of the two symmetrical and identical sections in the table, eliminating the products of 0 multiplier and 0 multiplicand, moving the product of the multiplier having an index of n into the location of index (n-1) for the multiplier, using one-half of the number of the largest multiplier as the largest multiplier index for the compressed multiplication table, moving into the non-continuous memory space of the compressed multiplication table by a page-filling method the product of the largest multiplier index value that is larger than the compressed multiplication table such that the multiplication table after compression can be stored on the same page.
摘要翻译：一种压缩整数乘法表的方法，包括以下步骤：首先消除表中两个对称和相同部分之一，消除0乘法器和0乘法器的乘积，将具有索引为n的乘法器的乘积移动到位置（n-1），使用最大乘数的数目的一半作为压缩乘法表的最大乘数索引，通过页面转换到压缩乘法表的非连续存储器空间中，填充方法是大于压缩乘数表的最大乘数指数值的乘积，使得压缩后的乘法表可以存储在同一页上。

35. 发明授权

US5737212A Flag setting circuit for microcontroller 失效
标题翻译：微控制器的标志设置电路
公开(公告)号：US5737212A
公开(公告)日：1998-04-07
申请号：US567146
申请日：1995-12-04
申请人： I Liang Fang , Kuo Cheng Yu , Jason Chen
发明人： I Liang Fang , Kuo Cheng Yu , Jason Chen
IPC分类号： G06F9/30 , G06F11/00 , G05B19/048
CPC分类号： G06F9/30083 , G06F11/0757 , G06F9/30076 , G06F9/30079
摘要： A flag setting circuit for a microcontroller, which can be set with a HALT mode flag and a watchdog timer overflow flag by using a system power-on signal, an external reset signal, a watchdog timer overflow signal inside the microcontroller, a clear instruction for watchdog timer, a HALT mode instruction, and a wake-up signal. The setting circuit for the watchdog timer overflow flag includes a reset signal generator, a watchdog timer, a clear signal generator, a flag clear circuit, and a register circuit. The setting circuit for the HALT mode flag includes a HALT mode discerning circuit, a flag clear circuit, and a register circuit. The frequency source of the watchdog timer is provided by means of a frequency from the system oscillator divided with four, or by using a frequency of RC oscillator built in the system. Under the HALT mode, the RC oscillator is selected. By means of the HALT mode flag and the watchdog timer overflow flag, the operation condition of the system hardware can be discerned.
摘要翻译：用于微控制器的标志设置电路，可以通过使用系统通电信号，外部复位信号，微控制器内部的看门狗定时器溢出信号，设置HALT模式标志和看门狗定时器溢出标志，清除指令看门狗定时器，HALT模式指令和唤醒信号。看门狗定时器溢出标志的设置电路包括复位信号发生器，看门狗定时器，清除信号发生器，标志清除电路和寄存器电路。用于HALT模式标志的设置电路包括HALT模式识别电路，标志清除电路和寄存器电路。看门狗定时器的频率源通过来自系统振荡器分频四个的频率，或通过使用内置于系统中的RC振荡器的频率来提供。在HALT模式下，选择RC振荡器。通过HALT模式标志和看门狗定时器溢出标志，可以看出系统硬件的运行状况。

36. 发明授权

US5694351A Method and apparatus for generating degree of membership in fuzzy inference 失效
标题翻译：产生模糊推理隶属度的方法和装置
公开(公告)号：US5694351A
公开(公告)日：1997-12-02
申请号：US611793
申请日：1996-03-06
申请人： George Chang , Paul Chen , Jason Chen
发明人： George Chang , Paul Chen , Jason Chen
IPC分类号： G06N7/04 , G06G7/00 , G06F15/18
CPC分类号： G06N7/04 , Y10S706/90
摘要： A method and apparatus for determining the degree of membership in a fuzzy inference by using a subtractor and a divider without the need for a complicated multiplication, division circuit or software that is normally required in a conventional method. A fuzzy inference database for the degree of membership is first established in a microprocessor by a fuzzy inference method, the membership function in the fuzzy database has a range between 0 to 1 at full scale for the degree of membership function. When the microprocessor detects an input data, a slope distance ratio and the corresponding coordinates are determined and compared using the input data and the fuzzy database established in the microprocessor. The ratio determined by the greatly simplified method is the degree of membership function.
摘要翻译：一种用于通过使用减法器和分频器来确定模糊推理的隶属程度的方法和装置，而不需要常规方法中通常需要的复杂的乘法，除法电路或软件。首先在微处理器中通过模糊推理方法建立了隶属程度的模糊推理数据库，模糊数据库中的隶属函数在隶属度函数的范围内范围为0到1。当微处理器检测到输入数据时，使用输入数据和微处理器中建立的模糊数据确定和比较相应的坐标。通过大大简化的方法确定的比例是隶属函数的程度。

37. 外观设计

USD320230S Hand-held motor-driven eraser 失效
公开(公告)号：USD320230S
公开(公告)日：1991-09-24
申请号：US349783
申请日：1989-05-09
申请人： Jason Chen
设计人： Jason Chen

38. 发明授权

US11249322B2 Glass-free 3D display system using dual image projection and tri-colors grating multiplexing panels 有权
公开(公告)号：US11249322B2
公开(公告)日：2022-02-15
申请号：US17117020
申请日：2020-12-09
申请人： John C. Pokotylo , Jason Chen
发明人： Duan-Jun Chen , Jason Chen
IPC分类号： G02B30/33 , G03B21/60 , G03B35/22
摘要： The problem of 3D panel display systems either (a) requiring special glasses to separate left and right viewing images, or (b) having auto-stereoscopic 3D with compromised fidelity, is solved by providing a projection three dimensional (3D) display system for providing glass-free, 3D display to a plurality of viewing volumetric pairs (VVAs) in space corresponding to a hypothetical plurality of viewers' eye aperture pairs, the projection 3D display system comprising: (a) a dual-image projector configured to project both a left viewing tri-color image and a right viewing tri-color image; and (b) means for (1) receiving a tri-color mixed input beam encompassing the left and right viewing tri-color images, (2) multiplying the tri-color mixed input beam into a plurality of tri-color mixed output beams, and (3) focusing the plurality of tri-color mixed beams for viewing at the VVAs.

39. 发明授权

US08911551B2 Electroless plating apparatus and method 有权
标题翻译：化学镀设备及方法
公开(公告)号：US08911551B2
公开(公告)日：2014-12-16
申请号：US13196179
申请日：2011-08-02
申请人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
发明人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
IPC分类号： B05C11/00 , C23C18/16 , H01L21/768 , H01L21/288
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1666 , C23C18/1669 , H01L21/76843
摘要： An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.
摘要翻译：公开了专门用于电镀至少一个半导体晶片的化学镀设备和方法。该装置包括容器，晶片保持器，电解质供给单元和超声波振动单元。容器设有至少一个入口并用于容纳电解质。晶片保持器设置在容器内。电解质供给单元用于经由入口将电解质供给到容器中。由至少一个频率超声波换能器组成的超声波振动单元设置在容器中，用于在容器中产生均匀的电解液流。因此，可以均匀地镀覆晶片，特别是对于具有精细通孔或沟槽结构的晶片。

40. 发明授权

US08762779B2 Multi-core processor with external instruction execution rate heartbeat 有权
标题翻译：具有外部指令执行率心跳的多核处理器
公开(公告)号：US08762779B2
公开(公告)日：2014-06-24
申请号：US12964949
申请日：2010-12-10
申请人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
发明人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/364 , G06F11/3652 , G06F11/3656
摘要： A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
摘要翻译：一种用于调试多核微处理器的方法包括使微处理器执行指令的实际执行，并从微处理器获得心跳信息，该信号指定多个核心相对于彼此的指令的实际执行顺序，命令相应的多个的核心的软件功能模型的实例，以根据由心跳信息指定的实际执行顺序来执行指令，以生成指令执行的模拟结果，并将模拟结果与指令执行的实际结果进行比较以确定它们是否匹配。每个核心输出指示执行指示符，指示核心每个核心时钟执行的指令数。心跳发生器为外部总线上的每个内核生成一个心跳指示符，指示每个外部总线时钟周期内由每个内核执行的指令数。

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