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31. 发明授权

US08044923B1 Backlight dimming and LCD amplitude boost 有权
公开(公告)号：US08044923B1
公开(公告)日：2011-10-25
申请号：US11955279
申请日：2007-12-12
申请人： Stephen D. Lew , Michael A. Ogrinc
发明人： Stephen D. Lew , Michael A. Ogrinc
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G3/3685 , G09G2320/0276 , G09G2320/0626 , G09G2320/064 , G09G2320/0646 , G09G2320/0653 , G09G2330/021 , G09G2360/16
摘要： Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

32. 发明授权

US08044922B1 Backlight dimming and LCD amplitude boost 有权
公开(公告)号：US08044922B1
公开(公告)日：2011-10-25
申请号：US11955271
申请日：2007-12-12
申请人： Stephen D. Lew , Michael A. Ogrinc
发明人： Stephen D. Lew , Michael A. Ogrinc
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G3/3685 , G09G2320/0276 , G09G2320/0626 , G09G2320/064 , G09G2320/0646 , G09G2320/0653 , G09G2330/021 , G09G2360/16
摘要： Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

33. 发明授权

US07965895B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07965895B1
公开(公告)日：2011-06-21
申请号：US11837336
申请日：2007-08-10
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

34. 发明授权

US07916153B1 Backlight dimming and LCD amplitude boost 有权
公开(公告)号：US07916153B1
公开(公告)日：2011-03-29
申请号：US11955276
申请日：2007-12-12
申请人： Stephen D. Lew , Michael A. Ogrinc
发明人： Stephen D. Lew , Michael A. Ogrinc
IPC分类号： G09G5/00 , G09G5/10 , G09G3/34 , G09G3/36 , H04N5/46 , H04N5/57 , G03F3/08
CPC分类号： G09G3/3406 , G09G3/3685 , G09G2320/0276 , G09G2320/0626 , G09G2320/064 , G09G2320/0646 , G09G2320/0653 , G09G2330/021 , G09G2360/16
摘要： Embodiments of the present invention generally provide m Methods and apparatus for reducing power consumption of backlit displays are described. Power consumption is reduced by dimming backlighting by a first scale factor and boosting pixel values by a second scale factor to compensate for the dimming. The scale factors may be constant values. Alternately, one or both of the scale factors may be determined based on pixel values for one or more frames to be displayed and/or one or more frames that have been displayed. For example, scale factors may be calculated based on an average linear amplitude of one or more frames of pixel values or from a maximum pixel value of one or more frames of pixel values. A graphical processing system is described including an integrated circuit capable of transforming a pixel value from a gamma-compensated space to a linear space.

35. 发明授权

US07624224B1 System and method for directly executing code from block-based memory 有权
标题翻译：从基于块的内存直接执行代码的系统和方法
公开(公告)号：US07624224B1
公开(公告)日：2009-11-24
申请号：US11301650
申请日：2005-12-13
申请人： Shang-Tse Chuang , Stephen D. Lew , Gerrit A. Slavenburg
发明人： Shang-Tse Chuang , Stephen D. Lew , Gerrit A. Slavenburg
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/44505 , G06F2212/2022
摘要： A system, method, and computer program product are provided for directly executing code in block-based memory, which resides in communication with a processor and a controller. Utilizing the controller, a request is received from the processor for a subset of a block of data in the block-based memory, and at least a portion of the block is retrieved from the block-based memory. After the retrieval, at least a portion of the block is stored in a cache. The subset of the block is then transmitted to the processor, utilizing the controller. To this end, code in the block-based memory is directly executed.
摘要翻译：提供了一种用于在基于块的存储器中直接执行代码的系统，方法和计算机程序产品，其驻留在与处理器和控制器的通信中。利用控制器，从处理器接收基于块的存储器中的数据块的子集的请求，并且从基于块的存储器检索块的至少一部分。在检索之后，块的至少一部分被存储在高速缓存中。然后利用控制器将块的子集发送到处理器。为此，直接执行基于块的内存中的代码。

36. 发明授权

US07526634B1 Counter-based delay of dependent thread group execution 有权
标题翻译：依赖线程组执行的基于计数器的延迟
公开(公告)号：US07526634B1
公开(公告)日：2009-04-28
申请号：US11535871
申请日：2006-09-27
申请人： Jerome F. Duluk, Jr. , Stephen D. Lew , John R. Nickolls
发明人： Jerome F. Duluk, Jr. , Stephen D. Lew , John R. Nickolls
IPC分类号： G06F9/40
CPC分类号： G06F9/52 , G06F9/546 , G06F2209/548
摘要： Systems and methods for synchronizing processing work performed by threads, cooperative thread arrays (CTAs), or “sets” of CTAs. A central processing unit can load launch commands for a first set of CTAs and a second set of CTAs in a pushbuffer, and specify a dependency of the second set upon completion of execution of the first set. A parallel or graphics processor (GPU) can autonomously execute the first set of CTAs and delay execution of the second set of CTAs until the first set of CTAs is complete. In some embodiments the GPU may determine that a third set of CTAs is not dependent upon the first set, and may launch the third set of CTAs while the second set of CTAs is delayed. In this manner, the GPU may execute launch commands out of order with respect to the order of the launch commands in the pushbuffer.
摘要翻译：由线程执行的处理工作同步的系统和方法，协同线程数组（CIA）或CTA的“集合”。中央处理单元可以加载针对第一组CTA和第二组CTA的推送命令，并且在第一组的执行完成时指定第二组的依赖关系。并行或图形处理器（GPU）可以自主地执行第一组CTA并且延迟第二组CTA的执行，直到第一组CTA完成。在一些实施例中，GPU可以确定第三组CTA不依赖于第一组，并且可以启动第三组CTA，同时第二组CTA被延迟。以这种方式，GPU可以相对于推送缓冲器中的发射命令的顺序执行命令无序。

37. 发明授权

US07466316B1 Apparatus, system, and method for distributing work to integrated heterogeneous processors 有权
标题翻译：用于将工作分配到集成异构处理器的装置，系统和方法
公开(公告)号：US07466316B1
公开(公告)日：2008-12-16
申请号：US11012390
申请日：2004-12-14
申请人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
发明人： Jonah M. Alben , Stephen D. Lew , Paolo E. Sabella
IPC分类号： G06F15/00 , G06F15/16 , G06F15/80 , G06F13/14 , G06F15/76 , G06F9/44 , G06T1/00 , G06T1/20 , G09G5/39 , G09G5/36
CPC分类号： G06F15/16 , G06F9/5044 , G06T1/20 , G06T15/005 , G09G5/363 , G09G2330/021 , G09G2360/06 , Y02D10/22
摘要： An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.
摘要翻译：集成电路包括至少两种不同类型的处理器，诸如图形处理器和视频处理器。通常由两种不同类型的处理器支持至少一种操作。对于被调度的每个通常支持的操作，作出决定以确定将选择哪种类型的处理器来实现该操作。

38. 发明授权

US08520009B1 Method and apparatus for filtering video data using a programmable graphics processor 有权
公开(公告)号：US08520009B1
公开(公告)日：2013-08-27
申请号：US12649188
申请日：2009-12-29
申请人： Stephen D. Lew , Garry W. Amann , Hassane S. Azar
发明人： Stephen D. Lew , Garry W. Amann , Hassane S. Azar
IPC分类号： G06T1/20
CPC分类号： H04N19/86 , H04N7/01 , H04N7/012
摘要： Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.

39. 发明授权

US08253750B1 Digital media processor 有权
标题翻译：数字媒体处理器
公开(公告)号：US08253750B1
公开(公告)日：2012-08-28
申请号：US12832830
申请日：2010-07-08
申请人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
发明人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
IPC分类号： G06F13/14 , G06F15/80 , G06F15/00
CPC分类号： G06T15/005 , G06F15/78 , G09G5/003 , G09G2360/02 , H04N13/161
摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.
摘要翻译：为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如作为电视机，显示器和网络设备，如打印机和网络录像机。本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

40. 发明授权

US08099584B2 Methods for scalably exploiting parallelism in a parallel processing system 有权
标题翻译：在并行处理系统中可扩展地利用并行性的方法
公开(公告)号：US08099584B2
公开(公告)日：2012-01-17
申请号：US13099035
申请日：2011-05-02
申请人： John R. Nickolls , Stephen D. Lew
发明人： John R. Nickolls , Stephen D. Lew
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3012 , G06F9/3889 , G06F9/5066
摘要： Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation.
摘要翻译：并行处理子系统中的并行性以可扩展的方式被利用。要解决的问题可以被分层分解成至少两个级别的子问题。定义程序执行的各个线程来解决最低级别的问题。线程被分组成一个或多个线程数组，每个线程数组都解决了较高级的子问题。线程数组可以通过处理内核执行，每个核心可以一次执行至少一个线程数组。线程数组可以分组成独立线程数组的网格，从而解决更高级的子问题或整个问题。网格中的线程数组或整个网格可以分布在所有可用处理核心中，如特定系统实现中可用的。

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