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31. 发明申请

US20090235038A1 HYBRID MEMORY SYSTEM WITH BACKUP POWER SOURCE AND MULTIPLE BACKUP AN RESTORE METHODOLOGY 有权
标题翻译：具有备份电源的混合存储器系统和多个备份恢复方法
公开(公告)号：US20090235038A1
公开(公告)日：2009-09-17
申请号：US12471400
申请日：2009-05-24
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F12/16
CPC分类号： G06F11/1441 , G06F12/0638
摘要： A memory subsystem includes a volatile memory and a nonvolatile memory. A controller includes logic to interface the volatile memory to an external system, so that the volatile memory is addressable for reading and writing by the external system. The controller includes logic to back up data from the volatile memory to the nonvolatile memory upon receiving a backup signal from the external system. A power controller includes logic to detect when power from the external system fails, and when power from the external system fails, to provide backup power for long enough to enable the controller to back up data from the volatile memory to a first region of the nonvolatile memory. The controller, upon receiving the backup signal from the external system, backs up data from the volatile memory to a second region of the nonvolatile memory different that the first region used to back up data from the volatile memory to the nonvolatile memory when power from the external system fails.
摘要翻译：存储器子系统包括易失性存储器和非易失性存储器。控制器包括将易失性存储器连接到外部系统的逻辑，使得易失性存储器可寻址以供外部系统读取和写入。该控制器包括在从外部系统接收到备用信号时将数据从易失性存储器备份到非易失性存储器的逻辑。功率控制器包括用于检测来自外部系统的电力何时故障的逻辑，以及当来自外部系统的电力发生故障时，提供足够长的备用电力以使得控制器能够将数据从易失性存储器备份到非易失性存储器的第一区域记忆。控制器在接收到来自外部系统的备份信号时，将数据从易失性存储器备份到非易失性存储器的第二区域，其不同之处在于，当来自该存储器的电源从第一区域用于将数据从易失性存储器备份到非易失性存储器时外部系统失败。

32. 发明申请

US20090031099A1 Power interrupt recovery in a hybrid memory subsystem 有权
标题翻译：混合存储器子系统中的电源中断恢复
公开(公告)号：US20090031099A1
公开(公告)日：2009-01-29
申请号：US11881361
申请日：2007-07-25
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G11C5/143 , G11C5/144 , Y02D10/13
摘要： A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.
摘要翻译：存储器子系统包括易失性存储器和非易失性存储器，以及用于在检测到系统电源的恢复时中断存储器子系统的掉电保存操作的逻辑，并且如果足够的非易失性存储器容量内存子系统可用于备份内存子系统的易失性内存容量。

33. 发明申请

US20090031098A1 Variable partitioning in a hybrid memory subsystem 有权
标题翻译：混合内存子系统中的可变分区
公开(公告)号：US20090031098A1
公开(公告)日：2009-01-29
申请号：US11881248
申请日：2007-07-25
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F12/16
CPC分类号： G06F12/0638 , G06F11/1441 , G06F11/1451 , G06F13/4239 , G11C5/143 , G11C5/144
摘要： A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
摘要翻译：存储器子系统可以包括逻辑，使得可以向其安装易失性存储器的至少一部分的设备提供可用于在设备电源故障的情况下被备份到非易失性存储器的设备。该逻辑可能使设备在易失性存储器的至少一部分可用于在设备电源故障的情况下不被备份到非易失性存储器，并且使该设备至少一部分非易失性存储器是可用的不保留用于来自易失性存储器的备份。

34. 发明授权

US07370140B2 Enhanced DRAM with embedded registers 失效
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US07370140B2
公开(公告)日：2008-05-06
申请号：US09962287
申请日：2001-09-24
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
IPC分类号： G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

35. 发明授权

US06223266B1 System and method for interfacing an input/output system memory to a host computer system memory 失效
标题翻译：用于将输入/输出系统存储器连接到主机系统存储器的系统和方法
公开(公告)号：US06223266B1
公开(公告)日：2001-04-24
申请号：US08914960
申请日：1997-08-20
申请人： Ronald H. Sartore
发明人： Ronald H. Sartore
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.
摘要翻译：提供了一种用于在包括本地计算机总线的输入/输出系统，连接到本地计算机总线的处理器和与计算机系统总线的接口以及具有主存储器的计算机系统之间进行接口的系统和方法。该系统包括具有控制数据的访问和存储的存储器控制器的存储器系统。预期由处理器对数据的随机访问请求，系统可以通过计算机总线从计算机系统启动顺序或突发排序的数据块。还提供了一种用于将多个处理器连接到具有系统总线和主存储器的计算机系统的系统和方法。

36. 发明授权

US5721862A Enhanced DRAM with single row SRAM cache for all device read operations 失效
标题翻译：具有单行SRAM缓存的增强型DRAM，用于所有器件读取操作
公开(公告)号：US5721862A
公开(公告)日：1998-02-24
申请号：US460665
申请日：1995-06-02
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register. Additionally, the row registers/memory cache is sized to contain a row of data of the DRAM array. Furthermore, a single column decoder addresses corresponding locations in both the memory cache and the DRAM array. And finally, all reads are only from the memory cache.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。另外，行寄存器/存储器高速缓冲存储器的大小可以包含DRAM阵列的一行数据。此外，单列解码器解决存储器高速缓存和DRAM阵列中的相应位置。最后，所有的读取只能从内存缓存中读取。

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