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31. 发明授权

US06816962B2 Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions 失效
标题翻译：将非法OP代码重新编码为单个非法OP代码以适应与预解码指令相关联的额外位
公开(公告)号：US06816962B2
公开(公告)日：2004-11-09
申请号：US10082085
申请日：2002-02-25
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/3017 , G06F9/30181
摘要： A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.
摘要翻译：一种用于利用非法操作码集合中的比特的方法和系统，以便能够将预解码的指令存储在指令高速缓存中，而不增加表示预解码指令所需的比特数。在从存储器获取指令时，检查操作码是否存在非法操作码集合中的成员资格。如果指令操作代码是该集合的成员，则该指令可能被重新编码以使用不同的，常见的非法操作码。如果指令操作码不是非法操作码集合的成员，而是以预解码格式代替存储在指令高速缓存中的指令，附加的预解码信息可以被存储在指令编码中利用由非法操作代码的重新编码已经腾出的操作代码空间的部分。

32. 发明授权

US06513134B1 System and method for tracing program execution within a superscalar processor 失效
标题翻译：用于跟踪超标量处理器中程序执行的系统和方法
公开(公告)号：US06513134B1
公开(公告)日：2003-01-28
申请号：US09397293
申请日：1999-09-15
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： H02H305
CPC分类号： G06F11/3632 , G06F11/3636
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. Various features, individually and in combination, provide a real-time trace-forward and trace-back capability with a minimal number of pins running at a minimal frequency relative to the processor.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。各种功能，单独和组合，提供实时跟踪和追溯功能，最少数量的引脚以相对于处理器的最小频率运行。

33. 发明授权

US06560677B1 Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory 失效
标题翻译：方法，缓存存储器，系统和计算机程序产品，用于在关联高速缓冲存储器中存储瞬态，正常和锁定条目
公开(公告)号：US06560677B1
公开(公告)日：2003-05-06
申请号：US09304664
申请日：1999-05-04
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F12/0864 , G06F12/121 , G06F12/126 , G06F12/128
摘要： Ways of a cache memory system are designated as being in one of three subsets: a normal subset, a transient subset, and a locked subset. The designation of the respective subsets is provided by a normal subset floor index, a transient subset floor index, and a transient subset ceiling index. The respective indexes are used to select the subset into which new entries are copied from main memory as a result of a cache miss. If the new entry is designated as being characterized by normal program behavior, it is copied into the normal subset in the cache. If the new entry is designated as being characterized by transient program behavior, it is copied into the transient subset in the cache. The relationship between the normal subset and the transient subset is programmable. For example, the normal and the transient subsets may include at least one common way of the cache memory or the transient subset may be completely included in the normal subset or completely separate therefrom.
摘要翻译：缓存存储器系统的方式被指定为三个子集之一：正常子集，瞬变子集和锁定子集。相应子集的指定由正常子集层索引，瞬时子集底层索引和瞬时子集上限索引提供。相应的索引用于选择由于高速缓存未命中而从主存储器复制新条目的子集。如果新条目被指定为通过正常程序行为表征，则将其复制到缓存中的正常子集中。如果新条目被指定为由瞬时程序行为表征，则将其复制到缓存中的瞬态子集中。正常子集与瞬态子集之间的关系是可编程的。例如，正常和瞬态子集可以包括高速缓冲存储器的至少一种常见方式，或者瞬态子集可以完全包含在正常子集中或与其完全分开。

34. 发明授权

US6081860A Address pipelining for data transfers 失效
标题翻译：地址流水线进行数据传输
公开(公告)号：US6081860A
公开(公告)日：2000-06-27
申请号：US975545
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.
摘要翻译：一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

35. 发明授权

US5996092A System and method for tracing program execution within a processor before and after a triggering event 失效
标题翻译：在触发事件之前和之后跟踪处理器内的程序执行的系统和方法
公开(公告)号：US5996092A
公开(公告)日：1999-11-30
申请号：US760553
申请日：1996-12-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令。

36. 发明授权

US5809293A System and method for program execution tracing within an integrated processor 失效
标题翻译：集成处理器内程序执行跟踪的系统和方法
公开(公告)号：US5809293A
公开(公告)日：1998-09-15
申请号：US283128
申请日：1994-07-29
申请人： Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Joseph Irene , Harry I. Linzer , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Joseph Irene , Harry I. Linzer , Thomas Andrew Sartorius
IPC分类号： G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3648 , G06F2201/865
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。使用FIFO和串行逻辑电路来最小化从芯片广播信息所需的芯片引脚数。跟踪技术利用指令和数据断点调试功能来发出跟踪事件发生的外部跟踪工具。

37. 发明申请

US20090313695A1 Methods and Systems for Checking Run-Time Integrity of Secure Code Cross-Reference to Related Applications 有权
标题翻译：用于检查安全代码交叉引用到相关应用程序的运行时完整性的方法和系统
公开(公告)号：US20090313695A1
公开(公告)日：2009-12-17
申请号：US12485089
申请日：2009-06-16
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目是无效的，导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

38. 发明授权

US08639943B2 Methods and systems for checking run-time integrity of secure code cross-reference to related applications 有权
标题翻译：用于检查安全代码的运行时完整性的方法和系统交叉引用到相关应用程序
公开(公告)号：US08639943B2
公开(公告)日：2014-01-28
申请号：US12485089
申请日：2009-06-16
申请人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
发明人： Jeffrey Todd Bridges , Thomas Andrew Sartorius , Steven M. Millendorf
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目是无效的，导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

39. 发明授权

US07281118B2 Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor 失效
标题翻译：发送使用DCR命令生成的线程消息指向消息控制块在多处理器中存储消息和响应存储器地址
公开(公告)号：US07281118B2
公开(公告)日：2007-10-09
申请号：US11198042
申请日：2005-08-05
申请人： Jeffrey Todd Bridges , Gordon Taylor Davis , Thomas Andrew Sartorius , Michael Steven Siegel
发明人： Jeffrey Todd Bridges , Gordon Taylor Davis , Thomas Andrew Sartorius , Michael Steven Siegel
IPC分类号： G06F15/167
CPC分类号： G06F13/28
摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.
摘要翻译：用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。消息由消息控制块中包含的信息构建或传送到处理器或协处理器。处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

40. 发明授权

US06826747B1 System and method for tracing program instructions before and after a trace triggering event within a processor 失效
标题翻译：在处理器内跟踪触发事件之前和之后跟踪程序指令的系统和方法
公开(公告)号：US06826747B1
公开(公告)日：2004-11-30
申请号：US09412124
申请日：1999-10-05
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas K. Collopy , James N. Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F1130
CPC分类号： G06F11/3466
摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event, and then providing the trace information externally from the processor.
摘要翻译：一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。跟踪技术监视来自代码的正常执行流的指令流程的变化。跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令，然后从处理器向外部提供跟踪信息。

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