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31. 发明授权

US07445132B1 System for determining gas cartridge actuation state 失效
标题翻译：用于确定气瓶致动状态的系统
公开(公告)号：US07445132B1
公开(公告)日：2008-11-04
申请号：US11217857
申请日：2005-08-24
申请人： Michael W. Williams
发明人： Michael W. Williams
IPC分类号： B67D5/00
CPC分类号： F41B11/62
摘要： A gas cartridge actuation state determination system includes a puncture pin adapted to abut an end of the gas cartridge. A load sensor coupled to and in line with the puncture pin. A spring bears against the load sensor. The spring's force is such that it is insufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has not been punctured, but is sufficient to cause the puncture pin to be driven through the end of the gas cartridge when the end has already been punctured. In addition, the spring's force is such that it will be approximately zero after the puncture pin has been driven through the end that has already been punctured. A device coupled to the load sensor determines when the spring force is approximately zero.
摘要翻译：气体盒致动状态确定系统包括适于邻接气体盒的端部的穿刺销。耦合到穿刺针并与穿刺针一致的负载传感器。弹簧靠在负载传感器上。弹簧的力不足以使得当端部未被刺穿时，穿刺针被驱动通过气体盒的端部，但是足以使穿刺针被驱动通过气体盒的端部当结束已经被刺穿了。此外，弹簧的力使得在穿刺针被驱动穿过已经被刺穿的端部之后，弹簧的力将接近于零。耦合到负载传感器的装置确定弹簧力何时近似为零。

32. 发明授权

US07353329B2 Memory buffer device integrating refresh logic 有权
标题翻译：内存缓冲器集成刷新逻辑
公开(公告)号：US07353329B2
公开(公告)日：2008-04-01
申请号：US10674981
申请日：2003-09-29
申请人： Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman , John B. Halbert , Narendra S. Khandekar , Michael W. Williams
发明人： Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman , John B. Halbert , Narendra S. Khandekar , Michael W. Williams
IPC分类号： G06F12/16
CPC分类号： G11C11/406 , G06F13/1636 , G11C2211/4061
摘要： Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
摘要翻译：在存储器总线上没有活动的情况下，独立于存储器控制器，在与存储器件相关联的存储器控制器的存储器总线的时间内，独立于存储器控制器，在存储器件中的行存储器单元上执行刷新操作的装置和方法。

33. 发明授权

US06957307B2 Mapping data masks in hardware by controller programming 有权
标题翻译：通过控制器编程在硬件中映射数据掩码
公开(公告)号：US06957307B2
公开(公告)日：2005-10-18
申请号：US10104412
申请日：2002-03-22
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1668
摘要： A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.
摘要翻译：存储器控制器或其他设备可以用数据掩模映射方案来编程。存储器控制器内的选择设备可以用数据掩码映射方案设置在数据和数据掩码之间。在一个实施例中，可以使用数据掩模映射方案来包含存储设备并对其进行编程。

34. 发明授权

US06952367B2 Obtaining data mask mapping information 有权
标题翻译：获取数据掩码映射信息
公开(公告)号：US06952367B2
公开(公告)日：2005-10-04
申请号：US10701025
申请日：2003-11-03
申请人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
发明人： Robert J. Riesenman , James M. Dodd , Michael W. Williams
IPC分类号： G06F12/04 , G06F12/06 , G06F13/16 , G11C16/04
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
摘要翻译：数据掩模图可以以各种方式编程到存储设备中。在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。在另一个实施例中，从存储器中的位置检索数据掩码图。在另一个实施例中，通过算法确定数据掩码图。

35. 发明授权

US06862653B1 System and method for controlling data flow direction in a memory system 有权
标题翻译：用于控制存储系统中数据流方向的系统和方法
公开(公告)号：US06862653B1
公开(公告)日：2005-03-01
申请号：US09664516
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1673
摘要： A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data, address information and command information, to the memory devices and receives data from the memory devices. The buffering structure interconnects the memory device and the memory controller. The buffering structure is adapted to operate in a bi-directional manner for the direction of data flow therethrough. The data flow director, which may reside in the buffering structure, the memory controller, the memory devices, or an external device, controls the direction of data flow through the buffering structure based on the data transmitted from the memory controller or the memory device.
摘要翻译：提供了一种用于控制存储器系统中的数据流的方向的系统和方法。该系统包括存储器件，存储器控制器，缓冲结构和数据流导向器。存储器控制器将诸如读取数据，写入数据，地址信息和命令信息的数据发送到存储器件并从存储器件接收数据。缓冲结构将存储器件和存储器控制器互连。缓冲结构适于以双向方式操作数据流动的方向。可以驻留在缓冲结构中的数据流导向器，存储器控制器，存储器件或外部设备基于从存储器控制器或存储器件发送的数据来控制通过缓冲结构的数据流的方向。

36. 发明授权

US06772352B1 Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve 有权
标题翻译：如果速率超过基于温度曲线的阈值，则降低发出命令速率的方法和装置
公开(公告)号：US06772352B1
公开(公告)日：2004-08-03
申请号：US09677137
申请日：2000-09-29
申请人： Michael W. Williams , James M. Dodd
发明人： Michael W. Williams , James M. Dodd
IPC分类号： G06F1200
CPC分类号： G11C11/406
摘要： A method of issuing activate commands to a memory device includes issuing the activate commands to the memory device. A number of activate commands issued within a time period is counted. A determination is made as to whether the number of activate commands issued within the time period exceeds a threshold. The rate at which the activate commands are being issued is lowered if the number of activate commands being issued exceeds the threshold within the time period.
摘要翻译：向存储器件发出激活命令的方法包括向存储器件发出激活命令。对一段时间内发出的激活命令进行计数。确定在该时间段内发出的激活命令的数量是否超过阈值。如果发出的激活命令的数量在该时间段内超过阈值，则降低激活命令的发出速率。

37. 发明授权

US06553449B1 System and method for providing concurrent row and column commands 有权
标题翻译：提供并发行和列命令的系统和方法
公开(公告)号：US06553449B1
公开(公告)日：2003-04-22
申请号：US09675348
申请日：2000-09-29
申请人： James M. Dodd , Michael W. Williams
发明人： James M. Dodd , Michael W. Williams
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device. The communication paths further include a column command communication path that provides column commands to the memory devices, a column address communication path that provides column addresses for the column commands to the memory devices, a row command communication path that provides row commands to the memory devices, and a row address communication path that provides row addresses for the row commands to the memory device.
摘要翻译：提供了一种用于在存储器系统中提供并行列和行操作的系统和方法。存储器系统包括存储器控制器，多个存储器件以及存储器控制器和多个存储器件之间的通信路径。存储器控制器通过将存储器件提供列选择信号的通信路径和向存储器件提供行片选信号的通信路径耦合到每个存储器件。双芯片选择信号允许在存储设备中与行操作同时执行列操作。通信路径还包括向存储器件提供列命令的列命令通信路径，向存储器件提供列命令的列地址的列地址通信路径，向存储器件提供行命令的行命令通信路径以及行地址通信路径，其向行存储器设备提供行命令的行地址。

38. 发明申请

US20140108696A1 LOW SPEED ACCESS TO DRAM 审中-公开
标题翻译：低速访问DRAM
公开(公告)号：US20140108696A1
公开(公告)日：2014-04-17
申请号：US14132703
申请日：2013-12-18
申请人： David J. Zimmerman , Michael W. Williams
发明人： David J. Zimmerman , Michael W. Williams
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译：实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。

39. 发明授权

US07580465B2 Low speed access to DRAM 失效
标题翻译：低速访问DRAM
公开(公告)号：US07580465B2
公开(公告)日：2009-08-25
申请号：US11174424
申请日：2005-06-30
申请人： David J. Zimmerman , Michael W. Williams
发明人： David J. Zimmerman , Michael W. Williams
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译：实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。

40. 发明授权

US07013788B1 Launch tube with adjustable plenum 失效
标题翻译：发射管与可调气室
公开(公告)号：US07013788B1
公开(公告)日：2006-03-21
申请号：US10627104
申请日：2003-07-24
申请人： Michael W. Williams , Nicholas Bitsakis , Gary R. Berlam , James A. Lilley , Brenda Brennan MacLeod
发明人： Michael W. Williams , Nicholas Bitsakis , Gary R. Berlam , James A. Lilley , Brenda Brennan MacLeod
IPC分类号： F41F3/07
CPC分类号： F41F3/07 , F41A21/28
摘要： A launch tube assembly including an aft launch tube portion, a forward launch tube portion, and a transfer sleeve having a first end fixed to and adjacent the forward end of said aft launch tube portion and a second end adjustably receiving the forward launch tube portion. A forward end of the aft launch tube portion faces a rearward end of the forward launch tube portion within the transfer sleeve. An adjustable plenum is present having a volume within the transfer sleeve defined by an adjusted distance between the facing ends of aft and forward launch tube portions. An end cap is pinned to a forward end of the forward launch tube portion, a gas generator housed in the aft launch tube portion, and a countermeasure device is housed in the forward launch tube portion. An adjustably selected volume of the plenum is such that a gas generated by the gas generator will enable propulsion of the countermeasure device at a predetermined acceleration from the forward launch tube portion.
摘要翻译：一种发射管组件，包括后发射管部分，向前发射管部分和转移套筒，其具有固定到所述后部发射管部分的前端并邻近所述后部发射管部分的前端的第一端和可调节地接收所述向前发射管部分的第二端。后部发射管部分的前端面向传送套筒内的向前发射管部分的后端。存在可调整的通风室，其中传送套筒内的体积由后部的向前端和向前的发射管部分之间的调节距离限定。端盖固定在前发射管部分的前端，容纳在后发射管部分中的气体发生器，并且对向装置容纳在前发射管部分中。增压室的可调节选择的容积使得由气体发生器产生的气体将使得对策装置能够以预定加速度从前向发射管部分推进。

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