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31. 发明授权

US07943438B2 Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology 有权
标题翻译：用于SOI技术的可控硅整流器（SCR）结构的结构和方法
公开(公告)号：US07943438B2
公开(公告)日：2011-05-17
申请号：US12031084
申请日：2008-02-14
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H01L21/332
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

32. 发明授权

US07881028B2 E-fuse used to disable a triggering network 失效
标题翻译：用于禁用触发网络的电熔丝
公开(公告)号：US07881028B2
公开(公告)日：2011-02-01
申请号：US12041962
申请日：2008-03-04
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A device and/or circuit having an e-fuse is provided to disable a triggering network, and more specifically, an e-fuse is used to disable an electrostatic discharge (ESD) RC triggering network after device installation. The device and/or circuit includes a triggering network electrically coupled to an electrostatic discharge (ESD) protection device. An e-fuse is electrically coupled with the triggering network and configured to render the ESD protection device insensitive to a triggering signal after blowing the e-fuse.
摘要翻译：提供具有电子保险丝的装置和/或电路以禁用触发网络，更具体地，使用电子熔丝来在设备安装之后禁用静电放电（ESD）RC触发网络。该装置和/或电路包括电耦合到静电放电（ESD）保护装置的触发网络。电子熔丝与触发网络电耦合并且被配置为使得ESD保护装置在吹动电熔丝之后对触发信号不敏感。

33. 发明申请

US20110001551A1 CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE (E-FUSE) 有权
标题翻译：用于编程和重新编程低功耗，多种状态，电子保险丝（电子保险丝）的电路结构和方法
公开(公告)号：US20110001551A1
公开(公告)日：2011-01-06
申请号：US12496002
申请日：2009-07-01
申请人： Michel J. Abou-Khalil , Tom C. Lee , Junjun Li , Robert J. Gauthier, JR. , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Tom C. Lee , Junjun Li , Robert J. Gauthier, JR. , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01H37/76
CPC分类号： G11C17/16 , G11C11/5692 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L45/085 , H01L45/1206 , H01L45/14 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
摘要翻译：公开了电子熔丝编程/重新编程电路的实施例。在一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。使用电压源来改变施加到端子的电压的极性和可选的电压的大小，以便控制长导体层内的电子的双向流动，从而在长导体上形成开路和/或短路层 - 短导体层接口。可以使用这种打开和/或短路的形成来实现不同的编程状态。其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。还公开了相关联的电熔丝编程和重新编程方法的实施例。

34. 发明授权

US07772651B2 Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits 失效
标题翻译：绝缘体上半导体高压器件结构，制造这种器件结构的方法，以及高压电路的设计结构
公开(公告)号：US07772651B2
公开(公告)日：2010-08-10
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译：高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将每个栅电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

35. 发明授权

US07646573B2 Method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：改善ESD钳位装置触发和振荡抑制的方法
公开(公告)号：US07646573B2
公开(公告)日：2010-01-12
申请号：US12133424
申请日：2008-06-05
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

36. 发明授权

US07274546B2 Apparatus and method for improved triggering and leakage current control of ESD clamping devices 失效
标题翻译：用于改善ESD夹紧装置的触发和漏电流控制的装置和方法
公开(公告)号：US07274546B2
公开(公告)日：2007-09-25
申请号：US11162198
申请日：2005-08-31
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event includes a multiple stage triggering network configured between a pair of power rails, and a power clamp coupled to the multiple stage triggering network, the power clamp configured to discharge current from the ESD event. The multiple stage triggering network has a first control path and a second control path configured to individually control activation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）事件的装置包括配置在一对电源轨之间的多级触发网络和耦合到多级触发网络的功率钳，该电源钳被配置为从 ESD事件。多级触发网络具有被配置为单独地控制功率钳的激活的第一控制路径和第二控制路径。

37. 发明授权

US08737028B2 RC-triggered ESD clamp device with feedback for time constant adjustment 有权
标题翻译： RC触发ESD钳位装置，具有时间常数调整反馈
公开(公告)号：US08737028B2
公开(公告)日：2014-05-27
申请号：US13312047
申请日：2011-12-06
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译：用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。场效应晶体管与反相器的输出端相连。响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

38. 发明授权

US08692291B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08692291B2
公开(公告)日：2014-04-08
申请号：US13431456
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。器件区域由绝缘体上半导体衬底的器件层的一部分组成。掺杂区域和阱的第一部分限定了结。阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

39. 发明授权

US08637353B2 Through silicon via repair 失效
标题翻译：通过硅片修复
公开(公告)号：US08637353B2
公开(公告)日：2014-01-28
申请号：US13013378
申请日：2011-01-25
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/82
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译：用于改变布线路径的电阻的方法和系统。将布线路径的电阻与目标电阻值进行比较。如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

40. 发明申请

US20130285211A1 DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES 有权
标题翻译：与FIN型场效应晶体管技术兼容的器件结构
公开(公告)号：US20130285211A1
公开(公告)日：2013-10-31
申请号：US13455732
申请日：2012-04-25
申请人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
发明人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
IPC分类号： H01L29/00 , G06F17/50 , H01L21/20
CPC分类号： H01L27/1211 , G06F17/5068 , H01L21/3086 , H01L21/845
摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
摘要翻译：鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。位于间隙中的是由第二半导体材料构成的层。

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