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31. 发明授权

US08448124B2 Post timing layout modification for performance 失效
标题翻译：发布时序布局修改的性能
公开(公告)号：US08448124B2
公开(公告)日：2013-05-21
申请号：US13236977
申请日：2011-09-20
申请人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
发明人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
摘要翻译：提供了一种用于性能的后期时序布局修改的机制。该机制基于路径级别的时序分析，选择性地应用布局修改。该机制仅将压力应用于处于设置关键路径的晶体管，而不对保持关键路径中的晶体管施加压力。该机制可以使用施加应力以提高晶体管在设置关键路径中的性能的方法，只要该应力不会改善保持关键路径中的相邻晶体管的性能即可。在一些情况下，该机制可以施加应力以改善设置关键路径中的晶体管的性能，同时降低保持关键路径中的晶体管的性能。

32. 发明授权

US08302062B2 Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US08302062B2
公开(公告)日：2012-10-30
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

33. 发明授权

US07761818B2 Obtaining a feasible integer solution in a hierarchical circuit layout optimization 失效
标题翻译：在分层电路布局优化中获得可行的整数解
公开(公告)号：US07761818B2
公开(公告)日：2010-07-20
申请号：US11782706
申请日：2007-07-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

34. 发明申请

US20100153892A1 METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US20100153892A1
公开(公告)日：2010-06-17
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

35. 发明申请

US20090031259A1 OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 失效
标题翻译：在分层电路布局优化中获得可行的整数解
公开(公告)号：US20090031259A1
公开(公告)日：2009-01-29
申请号：US11782706
申请日：2007-07-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

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