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31. 发明申请

US20100095254A1 SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN 失效
标题翻译：用于测试半导体设计的模式敏感算法的系统和方法
公开(公告)号：US20100095254A1
公开(公告)日：2010-04-15
申请号：US12631899
申请日：2009-12-07
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的系统和方法。该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

32. 发明授权

US07552417B2 System for search and analysis of systematic defects in integrated circuits 失效
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07552417B2
公开(公告)日：2009-06-23
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

33. 发明授权

US07404164B2 IC design modeling allowing dimension-dependent rule checking 有权
标题翻译： IC设计建模允许维度依赖的规则检查
公开(公告)号：US07404164B2
公开(公告)日：2008-07-22
申请号：US10708039
申请日：2004-02-04
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
摘要翻译：一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

34. 发明授权

US07353472B2 System and method for testing pattern sensitive algorithms for semiconductor design 有权
标题翻译：用于半导体设计测试模式敏感算法的系统和方法
公开(公告)号：US07353472B2
公开(公告)日：2008-04-01
申请号：US11202591
申请日：2005-08-12
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的系统和方法。该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

35. 发明授权

US07284230B2 System for search and analysis of systematic defects in integrated circuits 有权
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07284230B2
公开(公告)日：2007-10-16
申请号：US10605849
申请日：2003-10-30
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。执行电路设计和特征搜索的提取和索引处理。在提取和索引处理期间，建立了用于电路设计的窗口网格，并且将基本图案与每个窗体中的形状合并。通过查找基础图案和形状之间的交点，将每个窗口中的形状转换为特征向量。将特征向量聚类以产生特征向量的索引。在特征搜索期间，识别电路布局的缺陷区域窗口，并将基本图案与缺陷区域窗口中的形状合并。通过发现基础图案和形状之间的交点，将缺陷区域窗口中的形状转换为缺陷向量。使用来自特征向量索引的代表特征向量，找到与缺陷向量相似的特征向量。分析缺陷向量和特征向量之间的相似性和差异性。

36. 发明授权

US07685544B2 Testing pattern sensitive algorithms for semiconductor design 有权
标题翻译：用于半导体设计的测试模式敏感算法
公开(公告)号：US07685544B2
公开(公告)日：2010-03-23
申请号：US11947254
申请日：2007-11-29
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的计算机程序产品。程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

37. 发明申请

US20090294812A1 Optical Sensor Including Stacked Photosensitive Diodes 有权
标题翻译：包含堆叠感光二极管的光学传感器
公开(公告)号：US20090294812A1
公开(公告)日：2009-12-03
申请号：US12129714
申请日：2008-05-30
申请人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
发明人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14647 , H01L27/14609 , H01L27/14641 , H01L27/14683
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译：互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。感测装置可以在第一和第二光敏二极管之间共享。

38. 发明授权

US07584077B2 Physical design characterization system 有权
标题翻译：物理设计表征系统
公开(公告)号：US07584077B2
公开(公告)日：2009-09-01
申请号：US10710113
申请日：2004-06-18
申请人： Betty L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
发明人： Betty L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
摘要翻译：用于在芯片设计数据中定位和定义分离到特定几何形状或形状配置的过程敏感点的系统，方法和介质。一旦确定了系统过程敏感站点，就会通过设计检查器对物理设计数据进行编码和执行3D设计检查台。产生目标匹配形状并将其嵌入到设计数据中。过程敏感站点的图片，地图和坐标生成并发送到网站库以供参考。

39. 发明授权

US07577927B2 IC design modeling allowing dimension-dependent rule checking 失效
标题翻译： IC设计建模允许维度依赖的规则检查
公开(公告)号：US07577927B2
公开(公告)日：2009-08-18
申请号：US12186764
申请日：2008-08-06
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
摘要翻译：一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

40. 发明申请

US20080320421A1 FEATURE EXTRACTION THAT SUPPORTS PROGRESSIVELY REFINED SEARCH AND CLASSIFICATION OF PATTERNS IN A SEMICONDUCTOR LAYOUT 审中-公开
标题翻译：特征提取，支持进行精细化的搜索和分类在半导体布局中的图案
公开(公告)号：US20080320421A1
公开(公告)日：2008-12-25
申请号：US11765473
申请日：2007-06-20
申请人： David L. Demaris , Rouwaida N. Kanj , Daniel N. Maynard , Michael D. Monkowski
发明人： David L. Demaris , Rouwaida N. Kanj , Daniel N. Maynard , Michael D. Monkowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results.
摘要翻译：一种用于在VLSI设计布局中搜索和分类模式的系统，方法和程序产品。提供了一种方法，其包括使用二维（2D）低差异序列生成目标矢量; 识别设计布局中的布局区域; 生成布局区域的特征向量; 将目标矢量中的序列值的子集与特征向量中的序列值作为初始过滤器进行比较，其中用于比较的系统确定如果比较目标向量中的序列值子集，布局区域不包含匹配特征向量中的序列值低于阈值; 并输出搜索结果。

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