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31. 发明授权

US6049134A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳金属互连布局以实现全局平坦化的集成电路的掩模生成技术
公开(公告)号：US6049134A
公开(公告)日：2000-04-11
申请号：US15821
申请日：1998-01-29
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , H01L29/72 , H01L21/283
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

32. 发明授权

US5998293A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
标题翻译：具有气隙的集成电路的多层互连结构和分离互连级别的柱
公开(公告)号：US5998293A
公开(公告)日：1999-12-07
申请号：US67425
申请日：1998-04-28
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L21/283
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括跨越晶片彼此间隔开的柱。支柱放置在互连层之间或互连层和半导体衬底之间。支柱通过空气间隙彼此分开，使得互连级别内的每个导体彼此间隔着空气。此外，一个级别的互连中的每个导体在另一个互连级别内的每个导体间隔着空气。空气间隙在多电平互连结构内提供较小的层间和体积电容，并且较小的寄生电容值提供通过导体发送的信号的最小传播延迟和交叉耦合噪声。通过溶解牺牲电介质形成气隙，并且通过不仅在每个导体的上表面，而且侧壁上采用阳极氧化，防止导体在去除牺牲电介质的区域中弯曲或翘曲。上侧壁和侧壁阳极氧化提供了比仅仅将上表面或侧壁表面阳极氧化的更刚性的金属导体结构。因此，支柱可以进一步间隔开，并且向上覆的导体提供所有必要的支撑。

33. 发明授权

US5926717A Method of making an integrated circuit with oxidizable trench liner 失效
标题翻译：制造具有可氧化沟槽衬垫的集成电路的方法
公开(公告)号：US5926717A
公开(公告)日：1999-07-20
申请号：US763313
申请日：1996-12-10
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/762 , H01L21/76 , H01L21/62
CPC分类号： H01L21/76227
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在所述第一有源区和所述第二有源区之间的半导体衬底中形成沟槽。然后在所述沟槽上形成第一电介质层，并且在所述第一电介质层上沉积多晶硅层。然后将多晶硅层热氧化以形成第二介电层。优选地，第一电介质是厚度为40-500埃的热氧化物，其消耗小于200埃的所述第一有源区和所述第二活性区。多晶硅层优选为1000〜2000埃。

34. 发明授权

US5926713A Method for achieving global planarization by forming minimum mesas in large field areas 失效
标题翻译：通过在大场区域形成最小台面来实现全局平坦化的方法
公开(公告)号：US5926713A
公开(公告)日：1999-07-20
申请号：US923322
申请日：1997-09-04
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/336 , H01L21/762
CPC分类号： H01L29/66712 , H01L21/31053 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.
摘要翻译：提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。分离过程导致在宽隔离区域中形成间隔开的多个硅提升管。硅提升管之间的空间理想地适用于跨半导体形貌沉积的电介质的最佳填充，即在活性区域之间形成的硅提升板之间和之间。硅立管和在立管之间延伸的最佳尺寸的沟槽增强了沉积的电介质的平面性。沉积的电介质上表面包括具有最小高度差异的凹槽，其中凹槽在硅立管之间形成的沟槽的正上方紧密间隔开。可以通过化学机械抛光步骤容易地去除凹部，对抛光垫具有最小的变形，导致电介质上表面的全局平坦化。

35. 发明授权

US5924008A Integrated circuit having local interconnect for reducing signal cross coupled noise 失效
标题翻译：具有局部互连的集成电路，用于降低信号交叉耦合噪声
公开(公告)号：US5924008A
公开(公告)日：1999-07-13
申请号：US942248
申请日：1997-10-01
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.
摘要翻译：提供具有改进的互连结构的集成电路。互连结构包括总是保持在VDD或VSS（即接地）电平的功率耦合局部互连。局部互连在上覆互连的关键运行之下存在介电间隔距离。有源局部互连用于吸收临界导体的噪声瞬变，以确保连接到导体的电路不起作用。因此，局部互连沿着导体长度的大部分延伸，并且比其延伸的导体更宽或更窄。局部互连可以是多晶硅，掺杂多晶硅，多晶硅，难熔金属硅化物或多层难熔金属。

36. 发明授权

US5851913A Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process 失效
标题翻译：通过单个通孔蚀刻和单次填充工艺形成集成电路的多层互连结构的方法
公开(公告)号：US5851913A
公开(公告)日：1998-12-22
申请号：US655246
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/768 , H01L21/76807
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.
摘要翻译：提供了多层互连结构。多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。在任一情况下，通孔通过第一电介质形成到下面的导体。在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。

37. 发明授权

US5846876A Integrated circuit which uses a damascene process for producing staggered interconnect lines 失效
公开(公告)号：US5846876A
公开(公告)日：1998-12-08
申请号：US655244
申请日：1996-06-05
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/768 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

38. 发明授权

US5814555A Interlevel dielectric with air gaps to lessen capacitive coupling 失效
标题翻译：具有气隙的间隔电介质以减少电容耦合
公开(公告)号：US5814555A
公开(公告)日：1998-09-29
申请号：US658456
申请日：1996-06-05
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.
摘要翻译：布置在两层互连之间的半导体器件中的介电常数介电层的介电常数降低。电介质包括第一电介质层，优选地来自沉积在第一级互连上的硅烷源，以在相邻的第一互连结构之间的中点处形成气隙;第二电介质，其以间隔开的间隔跨越第二电介质包含气隙沟槽，以及形成的第三电介质在所述第二电介质上。在第三电介质上形成第二互连电平。

39. 发明授权

US5679605A Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process 失效
标题翻译：由单通道蚀刻和双重填充工艺形成的集成电路的多层互连结构
公开(公告)号：US5679605A
公开(公告)日：1997-10-21
申请号：US658458
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76877
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.
摘要翻译：提供了多层互连结构。多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。在任一情况下，通孔通过第一电介质形成到下面的导体。在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。

40. 发明授权

US6121631A Test structure to determine the effect of LDD length upon transistor performance 失效
标题翻译：测试结构，以确定LDD长度对晶体管性能的影响
公开(公告)号：US6121631A
公开(公告)日：2000-09-19
申请号：US267444
申请日：1999-03-12
申请人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L23/544 , H01L29/78 , H01L23/58 , H01L27/088 , H01L31/119
CPC分类号： H01L29/6659 , H01L22/34 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90
摘要： The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance. Source/drain regions are then formed within the substrate a spaced distance from the second gate conductor, the spaced distance being dictated by the second predefined thickness. The resulting transistors have a mutual source/drain region between them. More transistors may also be fabricated in a similar manner.
摘要翻译：本发明有利地提供了一种用于形成用于确定晶体管的LDD长度如何影响晶体管特性的测试结构的方法。在一个实施例中，提供了与第二多晶硅栅极导体横向间隔开的第一多晶硅栅极导体。栅极导体各自设置在位于硅基衬底之上的栅极氧化物上。将LDD植入物转移到衬底的暴露区域中，以在邻近栅极导体的衬底内形成LDD区域。然后将第一间隔物材料形成在两个栅极导体的侧壁表面上至第一预定义的厚度。源极/漏极区域仅在衬底内形成与第一栅极导体间隔开的距离，间隔距离由第一预定义厚度决定。第二间隔物材料横向地邻近第一间隔物材料形成为第二预定距离。源极/漏极区域然后在衬底内形成与第二栅极导体间隔开的距离，间隔距离由第二预定厚度决定。所得的晶体管在它们之间具有相互的源极/漏极区域。也可以以类似的方式制造更多的晶体管。

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