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31. 发明授权

US06249112B1 Voltage regulating circuit for a capacitive load 有权
标题翻译：用于容性负载的电压调节电路
公开(公告)号：US06249112B1
公开(公告)日：2001-06-19
申请号：US09608445
申请日：2000-06-29
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network. The voltage regulating circuit also includes a second field-effect transistor connected between the output node and the second terminal of the supply voltage generator, which has its gate terminal connected to a constant voltage generating circuit means.
摘要翻译：提出了一种用于容性负载的电压调节电路，其连接在电源电压发生器的第一和第二端子之间。调节电路具有输入端子和输出端子，并且包括具有连接到调节电路的输入端子的反相输入端子和连接到分压器的中间节点的非反相输入端子的运算放大器。分压器连接在与调节电路的输出端子连接的输出节点和电源电压发生器的第二端子之间。运算放大器在输出节点和电源电压发生器的第一端之间连接有用于驱动第一场效应晶体管的输出端子。运算放大器的输出端也通过补偿网络连接到输出节点。电压调节电路还包括连接在电源电压发生器的输出节点和第二端子之间的第二场效应晶体管，其栅极端子连接到恒压产生电路装置。

32. 发明授权

US06237104B1 Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权
标题翻译：方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器
公开(公告)号：US06237104B1
公开(公告)日：2001-05-22
申请号：US09222070
申请日：1998-12-29
申请人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
发明人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
IPC分类号： G06F1200
CPC分类号： G11C8/18 , G11C16/32
摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
摘要翻译：讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。逻辑和用于启动读取阶段。

33. 发明授权

US06181602B2 Device and method for reading nonvolatile memory cells 有权
标题翻译：用于读取非易失性存储单元的装置和方法
公开(公告)号：US06181602B2
公开(公告)日：2001-01-30
申请号：US09322460
申请日：1999-05-28
申请人： Giovanni Campardo , Rino Micheloni , Alfonso Maurelli
发明人： Giovanni Campardo , Rino Micheloni , Alfonso Maurelli
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062
摘要： A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.
摘要翻译：一种用于读取存储单元的方法，包括同时提供两个存储相应未知充电条件的存储器单元; 产生两个电量，每个电量与相应存储器单元的相应充电条件相关; 将两个电量相互比较; 并根据比较结果产生2位信号。读取电路包括并联的两个分支的双输入比较器，每个分支通过电流/电压转换器连接到相应的存储单元。双输入比较器和电流/电压转换器均包括低阈值晶体管。

34. 发明申请

US20110167206A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多级闪存存储器件的配置
公开(公告)号：US20110167206A1
公开(公告)日：2011-07-07
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F12/02
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

35. 发明申请

US20090262593A1 CIRCUIT AND METHOD FOR RETRIEVING DATA STORED IN SEMICONDUCTOR MEMORY CELLS 有权
标题翻译：用于检测存储在半导体存储器单元中的数据的电路和方法
公开(公告)号：US20090262593A1
公开(公告)日：2009-10-22
申请号：US12248843
申请日：2008-10-09
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04 , G11C16/06 , G11C5/14
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

36. 发明授权

US07474577B2 Circuit and method for retrieving data stored in semiconductor memory cells 有权
标题翻译：用于检索存储在半导体存储单元中的数据的电路和方法
公开(公告)号：US07474577B2
公开(公告)日：2009-01-06
申请号：US11444892
申请日：2006-05-31
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/04
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
摘要翻译：电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置一个目标值，对应于要在存储器单元上执行的操作。电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

37. 发明授权

US07394694B2 Flash memory device with NAND architecture with reduced capacitive coupling effect 有权
标题翻译：具有NAND架构的闪存器件具有降低的电容耦合效应
公开(公告)号：US07394694B2
公开(公告)日：2008-07-01
申请号：US11445491
申请日：2006-05-31
申请人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
发明人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复至少一组这些组。

38. 发明授权

US07382660B2 Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
标题翻译：用于访问闪存NAND型的多级非易失性存储器件的方法
公开(公告)号：US07382660B2
公开(公告)日：2008-06-03
申请号：US11458904
申请日：2006-07-20
申请人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
发明人： Angelo Bovino , Vincenzo Altieri , Roberto Ravasio , Rino Micheloni , Mario De Matteis
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5641
摘要： Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
摘要翻译：多级编程允许通过从第二位单独编程第一位来在选定单元中写入第一位和第二位。第一位的编程确定从第一阈值电平转换到第二阈值电平。第二位的编程需要初步读取以检测第一位是否已被修改，如果第一位已被修改并执行第二写入步骤，执行第一写入步骤以使单元进入第三阈值电压，以使所选择的如果第一位未被修改，则将单元转换为不同于第三阈值电平的第四阈值电压。为了增加读取和编程的可靠性，在第二部分的初步读取期间，读取结果被迫对应于第一阈值水平。

39. 发明申请

US20080123411A1 Page buffer for multi-level NAND electrically-programmable semiconductor memories 有权
标题翻译：多级NAND电可编程半导体存储器的页缓冲器
公开(公告)号：US20080123411A1
公开(公告)日：2008-05-29
申请号：US11821131
申请日：2007-06-21
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C7/1021 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3459 , G11C2211/5621
摘要： A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means for retrieving, from the selected memory cell, an indication of an existing data value already stored in the second group of data bits, receiving means for receiving an indication of a target data value to be stored in the first group of data bits of the selected memory cell, combining means activatable during a combining phase for combining the indication of the existing data value with the indication of the received target data value, so as to obtain a modified indication corresponding to a target programming state for the memory cell and conditioning means for causing a potential of the coupling line to take the program enabling potential or the program inhibition potential depending on the modified indication. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.
摘要翻译：提供了用于电可编程存储器的页面缓冲器。页面缓冲器包括多个存储器单元，对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储器单元中的数据位数N> = 2，其中数据位至少包括第一数据位组和第二数据位组以及至少一个具有与所选存储单元可操作地相关联的耦合线的读/写单元。读取/编程单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置，用于通过使所述耦合线选择性地启用所选存储单元的编程状态的改变在一个能够实现潜力和程序禁止潜力的程序中。编程状态改变使能装置包括读取装置，用于从所选择的存储器单元检索已经存储在第二组数据位中的现有数据值的指示，接收装置，用于接收要存储的目标数据值的指示所选择的存储器单元的第一组数据位，在组合阶段可激活的组合装置，用于组合现有数据值的指示与接收到的目标数据值的指示，以便获得对应于目标编程的修改指示用于存储单元的状态和调节装置，用于使耦合线的电位取决于经修改的指示使能电位或程序禁止电位。组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

40. 发明申请

US20070053227A1 High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
标题翻译：非挥发性浮栅存储器具有低输出纹波的高压开关
公开(公告)号：US20070053227A1
公开(公告)日：2007-03-08
申请号：US11437405
申请日：2006-05-19
申请人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C5/14
CPC分类号： H02M3/073 , G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H02M2003/077 , H03K3/356104 , H03K17/063 , H03K17/6872 , H03K17/6874
摘要： A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
摘要翻译：高压开关具有高电压输入端子，接收高电压和输出端子。具有控制端子的传输晶体管连接在高电压输入端子和输出端子之间。电荷泵型的倍压电路的输出端与控制端子连接。电压倍增电路是对称型的，具有第一和第二电荷存储装置，接收周期型的时钟信号，并且具有第一电路支路和第二电路支路，它们彼此对称并在相对于时钟信号的相位相反。

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