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31. 发明授权

US4974712A Fluid coupling device and improved valving therefor 失效
标题翻译：流体耦合装置和改进的阀门
公开(公告)号：US4974712A
公开(公告)日：1990-12-04
申请号：US406492
申请日：1989-09-13
申请人： Richard J. Brown
发明人： Richard J. Brown
IPC分类号： F01P7/08 , F16D35/00 , F16D35/02
CPC分类号： F16D35/023
摘要： A fluid coupling device is disclosed of the type including a valve plate (31) separating the fluid chamber into an operating chamber (33) and a reservoir chamber (35). The valve plate defines first and second fill openings (43a,43b), flow through which is controlled by a valve member (41) which rotates in the plane of the valve plate in response to variations in temperature. The first (43a) and second (43b) fill openings are disposed in generally the same region of the valve plate (31). The valve member (41) includes first (41a) and second (41b) port covering portions, disposed to cover the fill openings, when the valve member is in a disengaged condition, and to uncover the openings as the valve member moves toward an engaged condition. Having the fill openings in the same region of the valve plate substantially reduces the negative effects of errors in the concentricities of the valve arm, valve plate and the various parts of the device.

32. 发明授权

US09224828B2 Method and system for floating guard rings in gallium nitride materials 有权
标题翻译：氮化镓材料中浮动保护环的方法和系统
公开(公告)号：US09224828B2
公开(公告)日：2015-12-29
申请号：US13270606
申请日：2011-10-11
申请人： Andrew Edwards , Hui Nie , Isik C. Kizilyalli , Richard J. Brown , David P. Bour , Linda Romano , Thomas R. Prunty
发明人： Andrew Edwards , Hui Nie , Isik C. Kizilyalli , Richard J. Brown , David P. Bour , Linda Romano , Thomas R. Prunty
IPC分类号： H01L29/76 , H01L29/66 , H01L29/808 , H01L29/868 , H01L29/872 , H01L29/06 , H01L29/20
CPC分类号： H01L29/66143 , H01L21/26546 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/08 , H01L29/2003 , H01L29/404 , H01L29/66083 , H01L29/66204 , H01L29/66212 , H01L29/66416 , H01L29/66924 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.
摘要翻译：半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。半导体结构还包括耦合到III族氮化物衬底的第一表面的第一导电类型的III族氮化物外延层，电耦合到III族氮化物衬底的第二表面的第一金属结构和III族氮化物耦合到III族氮化物外延层的第二导电类型的外延结构。 III族氮化物外延结构包括至少一个边缘端接结构。

33. 发明授权

US09159784B2 Aluminum gallium nitride etch stop layer for gallium nitride based devices 有权
公开(公告)号：US09159784B2
公开(公告)日：2015-10-13
申请号：US13299227
申请日：2011-11-17
申请人： Linda Romano , Andrew P. Edwards , Richard J. Brown , David P. Bour , Hui Nie , Isik C. Kizilyalli , Thomas R. Prunty , Mahdan Raj
发明人： Linda Romano , Andrew P. Edwards , Richard J. Brown , David P. Bour , Hui Nie , Isik C. Kizilyalli , Thomas R. Prunty , Mahdan Raj
IPC分类号： H01L29/872 , H01L29/06 , H01L29/66 , H01L29/778 , H01L21/306 , H01L29/47 , H01L29/20 , H01L29/10
CPC分类号： H01L29/7787 , H01L21/30621 , H01L29/0615 , H01L29/0619 , H01L29/0657 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66212 , H01L29/66462 , H01L29/7786 , H01L29/872
摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

34. 发明授权

US08969912B2 Method and system for a GaN vertical JFET utilizing a regrown channel 有权
标题翻译：利用再生长通道的GaN垂直JFET的方法和系统
公开(公告)号：US08969912B2
公开(公告)日：2015-03-03
申请号：US13198659
申请日：2011-08-04
申请人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Linda Romano , David P. Bour , Richard J. Brown , Thomas R. Prunty
IPC分类号： H01L29/74 , H01L31/0328 , H01L29/80 , H01L29/76 , H01L21/8238 , H01L21/336 , H01L29/66 , H01L21/8252 , H01L27/06 , H01L29/808 , H01L29/10 , H01L29/20
CPC分类号： H01L29/66909 , H01L21/8252 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/66446 , H01L29/66924 , H01L29/8083
摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.
摘要翻译：垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点，以及包括耦合到漏极的第二III族氮化物材料的漂移区域。场效应晶体管还包括沟道区，该沟道区包括耦合到漏极并沿着垂直方向邻近漏极设置的第三III族氮化物材料，至少部分围绕沟道区的栅极区，具有耦合到漂移的第一表面区域和与栅极区域相对的栅极区域的一侧上的第二表面，以及电连接到栅极区域的栅极接触。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得在垂直III族氮化物场效应晶体管的操作期间的电流沿着垂直方向，并且沟道区域沿着第二表面的至少一部分延伸的门区域。

35. 发明授权

US08846482B2 Method and system for diffusion and implantation in gallium nitride based devices 有权
标题翻译：在氮化镓基器件中扩散和注入的方法和系统
公开(公告)号：US08846482B2
公开(公告)日：2014-09-30
申请号：US13240877
申请日：2011-09-22
申请人： David P. Bour , Richard J. Brown , Isik C. Kizilyalli , Thomas R. Prunty , Linda Romano , Andrew P. Edwards , Hui Nie , Mahdan Raj
发明人： David P. Bour , Richard J. Brown , Isik C. Kizilyalli , Thomas R. Prunty , Linda Romano , Andrew P. Edwards , Hui Nie , Mahdan Raj
IPC分类号： H01L21/8222 , H01L21/322 , H01L29/778 , H01L21/338 , H01L21/225 , H01L29/66 , H01L29/20 , H01L29/861 , H01L29/207 , H01L21/265 , H01L29/808 , H01L29/872
CPC分类号： H01L21/26546 , H01L21/0332 , H01L21/2258 , H01L21/266 , H01L21/3245 , H01L29/2003 , H01L29/207 , H01L29/66136 , H01L29/66143 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
摘要翻译：在III族氮化物衬底中形成掺杂区域的方法包括提供III族氮化物衬底并形成具有预定图案并与III族氮化物衬底的一部分耦合的掩模层。 III族氮化物衬底的特征在于第一导电类型，并且预定图案限定III族氮化物衬底的暴露区域。该方法还包括将III族氮化物衬底加热到预定温度，并将双前体气体放置在III族氮化物衬底的暴露区域附近。双前体气体包括氮源和掺杂剂源。该方法还包括将预定温度保持预定时间段，形成与III族氮化物衬底的暴露区域相邻的p型III族氮化物区域，以及去除掩模层。

36. 发明授权

US08829574B2 Method and system for a GaN vertical JFET with self-aligned source and gate 有权
标题翻译：具有自对准源极和栅极的GaN垂直JFET的方法和系统
公开(公告)号：US08829574B2
公开(公告)日：2014-09-09
申请号：US13334514
申请日：2011-12-22
申请人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
发明人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
IPC分类号： H01L29/808 , H01L21/335 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66924 , H01L21/027 , H01L21/283 , H01L21/308 , H01L29/1095 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66893 , H01L29/66909 , H01L29/66916 , H01L29/7832 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
摘要翻译：半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

37. 发明授权

US08749015B2 Method and system for fabricating floating guard rings in GaN materials 有权
标题翻译：在GaN材料中制造浮动保护环的方法和系统
公开(公告)号：US08749015B2
公开(公告)日：2014-06-10
申请号：US13299254
申请日：2011-11-17
申请人： Donald R. Disney , Andrew P. Edwards , Hui Nie , Richard J. Brown , Isik C. Kizilyalli , David P. Bour , Linda Romano , Thomas R. Prunty
发明人： Donald R. Disney , Andrew P. Edwards , Hui Nie , Richard J. Brown , Isik C. Kizilyalli , David P. Bour , Linda Romano , Thomas R. Prunty
IPC分类号： H01L29/06
CPC分类号： H01L21/761 , H01L21/2654 , H01L21/266 , H01L21/765 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/2003 , H01L29/402 , H01L29/66136 , H01L29/66212 , H01L29/6631 , H01L29/66909 , H01L29/8083 , H01L29/872
摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.
摘要翻译：一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二与第一导电类型相反的第二导电类型的GaN外延层。第二GaN外延层耦合到第一GaN外延层。该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

38. 发明申请

US20130299882A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE METALLIZATION 有权
标题翻译：具有自对准源金属化的GAN垂直JFET的方法和系统
公开(公告)号：US20130299882A1
公开(公告)日：2013-11-14
申请号：US13468332
申请日：2012-05-10
申请人： Donald R. Disney , Richard J. Brown , Hui Nie
发明人： Donald R. Disney , Richard J. Brown , Hui Nie
IPC分类号： H01L29/80 , H01L21/20
CPC分类号： H01L29/41741 , H01L29/2003 , H01L29/42316 , H01L29/66446 , H01L29/8083
摘要： A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
摘要翻译：半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。沟道结构包括第一III族氮化物外延材料，其特征在于一个或多个沟道侧壁。半导体器件还包括耦合到沟道结构的源极区域。源区包括第二III族氮化物外延材料。所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构，与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。电介质层的顶表面与源区的顶表面基本上共面。

39. 发明申请

US20130299873A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION 有权
标题翻译：具有自对准栅极金属化的GAN垂直JFET的方法和系统
公开(公告)号：US20130299873A1
公开(公告)日：2013-11-14
申请号：US13468325
申请日：2012-05-10
申请人： Donald R. Disney , Richard J. Brown , Hui Nie
发明人： Donald R. Disney , Richard J. Brown , Hui Nie
IPC分类号： H01L29/80 , H01L21/335
CPC分类号： H01L29/8083 , H01L29/2003 , H01L29/66909
摘要： A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.
摘要翻译：半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区，沟道区和延伸区的第一III族氮化物外延层。沟道区域通过漂移区域与III族氮化物衬底分离。通道区域的特征在于第一宽度。延伸区域通过沟道区域与漂移区域分离。延伸区域的特征在于小于第一宽度的第二宽度。半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层，耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构，以及栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

40. 发明申请

US20130161780A1 METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION 有权
公开(公告)号：US20130161780A1
公开(公告)日：2013-06-27
申请号：US13335329
申请日：2011-12-22
申请人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Richard J. Brown , Donald R. Disney
发明人： Isik C. Kizilyalli , Hui Nie , Andrew P. Edwards , Richard J. Brown , Donald R. Disney
IPC分类号： H01L29/868 , H01L21/20
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0649 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/6631 , H01L29/66924
摘要： A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

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