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31. 发明授权

US08397009B2 Interconnection network with dynamic sub-networks 失效
标题翻译：互联网络与动态子网络
公开(公告)号：US08397009B2
公开(公告)日：2013-03-12
申请号：US12792218
申请日：2010-06-02
申请人： Francois Jacquet
发明人： Francois Jacquet
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each interconnection sub-network including: at least one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits, the information transfer bus comprising a plurality of portions of signal transmission lines connected to each other through signal repeater devices, and a controller device that controls the signal repeater devices, at least one of the signal repeater devices is controlled to be active depending on a value of an addressing signal to be sent to the addressing bus by said one of the m first circuits to the controller device, where m and n are integer numbers greater than 1.
摘要翻译：一种具有m个第一电子电路和n个第二电子电路的互连网络，包括m个互连子网络，每个互连子网络包括：将至少一个寻址总线和一个信息传输总线连接到所有n个第二电路中的一个电路，包括通过信号中继器装置彼此连接的信号传输线路的多个部分的信息传送总线，以及控制信号中继器设备的控制器设备，至少一个信号中继器设备根据由m个第一电路中的一个发送到寻址总线的寻址信号的值到控制器装置，其中m和n是大于1的整数。

32. 发明申请

US20100265758A1 Method for implementing an SRAM memory information storage device 有权
标题翻译：用于实现SRAM存储器信息存储设备的方法
公开(公告)号：US20100265758A1
公开(公告)日：2010-10-21
申请号：US12829675
申请日：2010-07-02
申请人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
发明人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
摘要翻译：提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。

33. 发明申请

US20100165709A1 ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR 有权
标题翻译：稳定的SRAM存储单元电容板电压发生器
公开(公告)号：US20100165709A1
公开(公告)日：2010-07-01
申请号：US12645039
申请日：2009-12-22
申请人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
发明人： Kevin K. Walsh , Paul F. Gerrish , Larry E. Tyler , Mark A. Lysinger , David C. McClure , Francois Jacquet
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C5/14 , G11C5/147 , G11C11/417
摘要： An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
摘要翻译：具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。存储单元的两个反相器由正电压和低电压供电。两个电容器在公共节点处彼此连接。泄漏电流发生器耦合到公共节点。泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。

34. 发明授权

US07321506B2 Multivibrator protected against current or voltage spikes 有权
标题翻译：多谐振荡器可防止电流或电压尖峰
公开(公告)号：US07321506B2
公开(公告)日：2008-01-22
申请号：US11379720
申请日：2006-04-21
申请人： Philippe Roche , Francois Jacquet , Sylvain Clerc
发明人： Philippe Roche , Francois Jacquet , Sylvain Clerc
IPC分类号： G11C11/41
CPC分类号： H03K3/02335 , H03K3/0375
摘要： The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.
摘要翻译：多谐振荡器被保护以防止电流或电压尖峰，并且包括第一数据传输端口，其接收作为输入的多谐振荡器输入数据，以及连接在第一传输端口的输出侧的第一/主机锁存单元。包括第二/从属锁存单元，并且第二数据传送端口被放置在第一和第二锁存单元之间。每个锁存单元包含一组冗余数据存储节点。传输端口每个电路/用于将数据单独写入每个存储节点的设备。

35. 发明申请

US20080008020A1 Memory device with programmable control for activation of read amplifiers 有权
标题翻译：具有可编程控制的存储器件，用于激活读取放大器
公开(公告)号：US20080008020A1
公开(公告)日：2008-01-10
申请号：US11824948
申请日：2007-07-03
申请人： Francois Jacquet , Franck Genevaux
发明人： Francois Jacquet , Franck Genevaux
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C7/14 , G11C7/08
摘要： An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterised in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.
摘要翻译：本发明的实施例涉及包括由位于行和列的交点处的存储器单元组成的存储器平面的存储器件，以及设计成输出信号以激活布置在存储器中的列的底部的读取放大器的虚拟路径所述虚拟路径包括连接在两个虚拟位线之间的虚拟存储器单元，所述虚拟存储单元选择至少一个设计成对所述虚拟位线中的至少一个排放的虚拟单元，以及连接到所述两个虚拟位线的控制单元以产生所述激活信号其特征在于，所述设备包括对所选择的单元的数量进行编程以便至少对所述虚拟位线进行排放的装置，以调整所述激活信号输出的时间。

36. 发明授权

US07272775B2 Memory circuit comprising an error correcting code 有权
标题翻译：存储电路包括纠错码
公开(公告)号：US07272775B2
公开(公告)日：2007-09-18
申请号：US10453844
申请日：2003-06-03
申请人： Francois Jacquet , Jean-Pierre Schoellkopf
发明人： Francois Jacquet , Jean-Pierre Schoellkopf
IPC分类号： G11C29/42
CPC分类号： G06F11/1008 , G06F11/1048
摘要： A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.
摘要翻译：一种具有包括地址总线（102），输入数据总线（108）和输出数据总线（115）的纠错系统的存储器电路，该电路包括具有地址总线（113），数据总线 114）和包括编码器（107）的纠错电路。第一地址寄存器（104）连接到电路的输入地址总线，用于仅依次存储对应于存储器写入操作的地址。第二数据寄存器（105）连接到电路（108）的输入数据总线，用于存储发送到编码器（107）的数据。电路使得可以在存储器写入中引入一个周期的移位，而不修改读取，给编码器更多的时间来计算纠错码。

37. 发明授权

US07236031B2 Fast bistable circuit protected against random events 有权
标题翻译：快速双稳态电路可防止随机事件
公开(公告)号：US07236031B2
公开(公告)日：2007-06-26
申请号：US11159818
申请日：2005-06-23
申请人： Sylvain Clerc , Philippe Roche , Francois Jacquet
发明人： Sylvain Clerc , Philippe Roche , Francois Jacquet
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.
摘要翻译：双稳态电路包括具有耦合到第一反相器的输出的一个输入的第一反相器和电容反相电路。电容反相电路包括并联到输入端的电容反相电路和电容性反相电路的输出的第二反相器和电容电路。双稳态电路还包括开关，当开关接收到有效验证信号时或者如果不是将电容性反转电路的输出耦合到第一反相器的输入端，则将电容反转电路的输出与第一反相器的输入隔离第一台逆变器

38. 发明授权

US07221581B2 Memory with storage cells biased in groups 有权
标题翻译：具有存储单元偏差的存储器
公开(公告)号：US07221581B2
公开(公告)日：2007-05-22
申请号：US11274039
申请日：2005-11-14
申请人： Francois Jacquet , Florent Vautrin
发明人： Francois Jacquet , Florent Vautrin
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/417
摘要： A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their own biasing circuit (200) in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.
摘要翻译：存储电路包括以行和列排列的多个存储单元（100），从而形成存储矩阵。对应于相同位线（21-23）的存储单元（100）被划分成用于同一列的单元的几组（60-61），这些组具有它们自己的偏置电路（200），以便作用于逻辑电平低电压与链路晶体管的衬底电压之间的差异。当不选择存储单元时，偏置电路使得源极/漏极和衬底之间的电压等于负电压，以便使漏电流最小化。在读取操作期间，衬底电压和源极/漏极电压恢复到相同的电平，使得当链路晶体管导通时最大电流将流动。

39. 发明申请

US20060255870A1 MULTIVIBRATOR PROTECTED AGAINST CURRENT OR VOLTAGE SPIKES 有权
标题翻译：保护电流或电压SPIKES的多功能一体机
公开(公告)号：US20060255870A1
公开(公告)日：2006-11-16
申请号：US11379720
申请日：2006-04-21
申请人： Philippe Roche , Francois Jacquet , Sylvain Clerc
发明人： Philippe Roche , Francois Jacquet , Sylvain Clerc
IPC分类号： H03K3/06
CPC分类号： H03K3/02335 , H03K3/0375
摘要： The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.
摘要翻译：多谐振荡器被保护以防止电流或电压尖峰，并且包括第一数据传输端口，其接收作为输入的多谐振荡器输入数据，以及连接在第一传输端口的输出侧的第一/主机锁存单元。包括第二/从属锁存单元，并且第二数据传送端口被放置在第一和第二锁存单元之间。每个锁存单元包括一组冗余数据存储节点。传输端口每个电路/用于将数据单独写入每个存储节点的设备。

40. 发明授权

US07057955B2 Dynamically unbalanced sense amplifier 有权
标题翻译：动态不平衡感测放大器
公开(公告)号：US07057955B2
公开(公告)日：2006-06-06
申请号：US10860080
申请日：2004-06-03
申请人： Franck Genevaux , Francois Jacquet
发明人： Franck Genevaux , Francois Jacquet
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C2207/065
摘要： A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.
摘要翻译：连接到第一和第二位线的感测放大器包括用于将所述位线预充电到高电压的装置，用于将一个或另一个位线连接到存储器单元的装置，所述连接根据存储器单元的状态分别由第一和第二位线控制的高电压或电压降低的位线的保持，以及与第一和第二晶体管串联的用于通过晶体管控制的电流的可控制装置当两个位线的电压处于高电压时，连接到存储单元的位线大于通过另一个晶体管的电流。

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