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31. 发明申请

US20120292669A1 FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US20120292669A1
公开(公告)日：2012-11-22
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

32. 发明授权

US09041105B2 Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
标题翻译：集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构
公开(公告)号：US09041105B2
公开(公告)日：2015-05-26
申请号：US13553947
申请日：2012-07-20
申请人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
发明人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/088 , H01L27/12 , H01L21/84 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/84
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

33. 发明授权

US08921190B2 Field effect transistor and method of manufacture 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08921190B2
公开(公告)日：2014-12-30
申请号：US12099175
申请日：2008-04-08
申请人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L21/336 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
摘要翻译：提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。有源区具有不同于第一导电类型的第二导电类型。接触区域与有源区域电接触。该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

34. 发明申请

US20100248432A1 METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT 有权
标题翻译：形成用于集成电路的高压P-N结和设计结构的方法
公开(公告)号：US20100248432A1
公开(公告)日：2010-09-30
申请号：US12795108
申请日：2010-06-07
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/84 , G06F17/50
CPC分类号： H01L29/93
摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
摘要翻译：形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

35. 发明授权

US07804119B2 Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit 失效
标题翻译：具有超陡P-N结的器件结构，形成超陡P-N结的方法，以及集成电路的设计结构
公开(公告)号：US07804119B2
公开(公告)日：2010-09-28
申请号：US12099316
申请日：2008-04-08
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/108
CPC分类号： H01L29/93
摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.
摘要翻译：具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

36. 发明授权

US08399927B2 Semiconductor structure including a high performance fet and a high voltage fet on an SOI substrate 有权
标题翻译：包括在SOI衬底上的高性能fet和高电压fet的半导体结构
公开(公告)号：US08399927B2
公开(公告)日：2013-03-19
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/148
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

37. 发明授权

US08299561B2 Shielding for high-voltage semiconductor-on-insulator devices 有权
标题翻译：高压绝缘体上半导体器件屏蔽
公开(公告)号：US08299561B2
公开(公告)日：2012-10-30
申请号：US12764244
申请日：2010-04-21
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L21/70 , H01L23/53 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

38. 发明授权

US08299558B2 Self-aligned Schottky diode 有权
标题翻译：自对准肖特基二极管
公开(公告)号：US08299558B2
公开(公告)日：2012-10-30
申请号：US13197414
申请日：2011-08-03
申请人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/66
CPC分类号： H01L29/7839 , H01L21/26586 , H01L29/665 , H01L29/66643 , H01L29/66659
摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.
摘要翻译：肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构另一侧的掺杂保护环。肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。还提供了用于本发明的肖特基势垒二极管的设计结构。

39. 发明申请

US20120199906A1 SEMICONDUCTOR DEVICE INCLUDING HIGH FIELD REGIONS AND RELATED METHOD 有权
标题翻译：包括高场区域的半导体器件及相关方法
公开(公告)号：US20120199906A1
公开(公告)日：2012-08-09
申请号：US13023042
申请日：2011-02-08
申请人： William F. Clark, JR. , Yun Shi
发明人： William F. Clark, JR. , Yun Shi
IPC分类号： H01L29/772
CPC分类号： H01L29/78654 , H01L29/42384 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device is disclosed. In an embodiment, a semiconductor device includes a N-well within a P-well in a silicon layer, the silicon layer positioned atop a buried oxide layer of a silicon-on-insulator (SOI) substrate; a first source region and a second source region within a portion of the P-well; a first drain region and a second drain region within a portion of the P-well and within a portion of the N-well; and a gate positioned atop the N-well, wherein a lateral high field region is generated between the N-well and the P-well and a vertical high field region is generated between the gate and the N-well. A related method is disclosed.
摘要翻译：公开了一种半导体器件。在一个实施例中，半导体器件包括在硅层中的P阱内的N阱，所述硅层位于绝缘体上硅（SOI）衬底的掩埋氧化物层的顶部; 在P阱的一部分内的第一源极区域和第二源极区域; 在P阱的一部分内并在N阱的一部分内的第一漏极区域和第二漏极区域; 以及位于N阱顶部的栅极，其中在N阱和P阱之间产生横向高场区域，并且在栅极和N阱之间产生垂直高场区域。公开了相关方法。

40. 发明授权

US08216890B2 Lateral hyperabrupt junction varactor diode in an SOI substrate 有权
标题翻译： SOI衬底中的横向超破坏结变容二极管
公开(公告)号：US08216890B2
公开(公告)日：2012-07-10
申请号：US12550658
申请日：2009-08-31
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/336
CPC分类号： H01L29/93 , H01L29/7391
摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.
摘要翻译：变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。在第二掺杂半导体区域和第二电极之间形成超破坏结。栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。还提供了变容二极管的设计结构。

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