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31. 发明授权

US06313769B1 Baseband digital offset correction 有权
标题翻译：基带数字偏移校正
公开(公告)号：US06313769B1
公开(公告)日：2001-11-06
申请号：US09563874
申请日：2000-05-03
申请人： Mandell J. Mangahas , Ramin Khoini-Poorfard
发明人： Mandell J. Mangahas , Ramin Khoini-Poorfard
IPC分类号： H03M106
CPC分类号： H03M1/1019 , H03M1/66
摘要： A signal processing system includes a main digital-to-analog converter (DAC) for receiving a digital baseband signal and converting the digital signal into an analog signal. Also included in the system is a connection circuit for receiving the analog signal, and output terminal, and an analog filter coupled between the connection circuit and the output terminal for filtering the analog signal. The system includes a calibration circuit coupled between the connection circuit and the output terminal for setting an offset voltage level. The calibration circuit includes (a) an approximation circuit coupled to the output terminal and operable during a calibration mode to determine the offset voltage level and store the offset voltage level as a digital offset signal and (b) an offset DAC coupled between the connection circuit and the approximation circuit for converting the digital offset signal into the offset voltage level. The connection circuit, which is a node, subtracts the offset voltage level from the analog signal.
摘要翻译：信号处理系统包括用于接收数字基带信号并将数字信号转换为模拟信号的主数/模转换器（DAC）。该系统还包括用于接收模拟信号的连接电路和输出端子，以及耦合在连接电路和输出端子之间的模拟滤波器，用于对模拟信号进行滤波。该系统包括耦合在连接电路和输出端子之间的校准电路，用于设定偏移电压电平。校准电路包括（a）耦合到输出端并且可在校准模式期间操作以确定偏移电压电平并将偏移电压电平存储为数字偏移信号的近似电路，以及（b）耦合在连接电路以及用于将数字偏移信号转换为偏移电压电平的近似电路。作为节点的连接电路从模拟信号中减去偏移电压电平。

32. 发明授权

US06181212B2 Phase locked loop for generating two disparate, variable frequency signals 有权
标题翻译：锁相环产生两个不同的可变频率信号
公开(公告)号：US06181212B2
公开(公告)日：2001-01-30
申请号：US09238990
申请日：1999-01-28
申请人： Ramin Khoini-Poorfard , Hussein K. Mecklai
发明人： Ramin Khoini-Poorfard , Hussein K. Mecklai
IPC分类号： H03L7197
CPC分类号： H03C3/0933 , H03C3/40 , H03D7/163 , H03D7/165 , H03L7/1976 , H04B1/00 , H04B1/28 , H04B1/406
摘要： A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a &Sgr;/&Dgr; converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.
摘要翻译：一种用于使用单个锁相环产生两个不同频率参考信号的方法和装置。电路包括用于产生参考信号的本地振荡器和用于将参考信号与反馈信号进行比较的相位比较器。相位比较器的输出通过压控振荡器转换成所需输出频率的第一个。该信号也在SIGMA / DELTA转换器的控制下馈送到可变分频器电路，该转换器产生较低频率信号而不产生辅助频率音调。低频信号是输出频率的第二个。该信号也通过固定分频器反馈到相位比较器的第二输入端。

33. 发明授权

US6121827A Digital noise reduction in integrated circuits and circuit assemblies 有权
标题翻译：集成电路和电路组件中的数字降噪
公开(公告)号：US6121827A
公开(公告)日：2000-09-19
申请号：US293510
申请日：1999-04-15
申请人： Ramin Khoini-Poorfard , Lysander B. Lim
发明人： Ramin Khoini-Poorfard , Lysander B. Lim
IPC分类号： H01L23/50 , H01L25/00
CPC分类号： H01L23/50 , H01L24/49 , H01L2223/6611 , H01L2223/6688 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/14 , H01L2924/3025
摘要： A mixed signal integrated circuit board having decreased sensitivity of analog circuitry to digital circuitry noise is disclosed. In the mixed-signal integrated board of the present invention, a new (second) analog ground is created. This new analog ground is not limited by the manufacturing specification of connectivity to the substrate of the circuit board and is thereby free of transient noise generated by digital components on the board. In a mixed-signal integrated circuit board of the present invention, the new analog ground becomes the preferred ground and is utilized in many sensitive analog applications including voltage and current measurements. The new analog ground is easy to create as it does not involved complicated circuitry. The new analog ground may be created even after the initial circuit schematics has been created.
摘要翻译：公开了一种具有降低的模拟电路对数字电路噪声灵敏度的混合信号集成电路板。在本发明的混合信号集成电路板中，产生新的（第二）模拟地。这种新的模拟接地不受电路板基板的连接的制造规范的限制，从而不受板上数字部件产生的瞬态噪声的影响。在本发明的混合信号集成电路板中，新的模拟地被成为优选的地面，并被用于包括电压和电流测量在内的许多敏感的模拟应用中。新的模拟地线容易创建，因为它不涉及复杂的电路。即使在创建初始电路原理图之后，也可能会创建新的模拟地。

34. 发明授权

US5841382A Fast testing of D/A converters 失效
标题翻译：快速测试D / A转换器
公开(公告)号：US5841382A
公开(公告)日：1998-11-24
申请号：US820819
申请日：1997-03-19
申请人： Robert W. Walden , Ramin Khoini-Poorfard , William E. Burchanowski
发明人： Robert W. Walden , Ramin Khoini-Poorfard , William E. Burchanowski
IPC分类号： H03M1/10 , H03M1/68 , H03M1/76
CPC分类号： H03M1/109 , H03M1/685 , H03M1/765
摘要： Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.
摘要翻译：通过应用一种或多种不同的方法来加速数模转换器的测试。一种方法依赖于开关电容器，其在测试期间降低转换器的总体电容，从而减少每个代码值的建立时间。另一种方法使得每个测试步骤的持续时间是特定代码值的函数，而不是使用每个测试步骤的最坏情况建立时间。另一种方法使用非连续代码值序列来确定转换器中的每个开关是否功能。使用非连续代码值允许在转换器测试期间使用部分建立时间。可以使用每种方法来加速D / A转换器的测试，无论它们是线性还是折叠电阻串。

35. 发明授权

US08611844B2 Low noise amplifier and method of input impedance control for terrestrial and cable modes 有权
标题翻译：低噪声放大器和地面和电缆模式的输入阻抗控制方法
公开(公告)号：US08611844B2
公开(公告)日：2013-12-17
申请号：US13344227
申请日：2012-01-05
申请人： Yu Su , Mustafa H. Koroglu , Abhishek Kammula , Ramin Khoini-Poorfard
发明人： Yu Su , Mustafa H. Koroglu , Abhishek Kammula , Ramin Khoini-Poorfard
IPC分类号： H04B1/16
CPC分类号： H04N5/455 , H04B1/18 , H04H40/27 , H04N21/42607 , H04N21/6112 , H04N21/6118
摘要： A low noise amplifier (LNA) for use in a receiver circuit includes an adjustable impedance network including an input for receiving a radio frequency signal, a plurality of control inputs, and an output. The LNA further includes a controller coupled to the plurality of control inputs and configured to control an impedance of the adjustable impedance network. The controller controls the adjustable impedance network to provide a relatively low impedance in a terrestrial mode and to provide a relatively high impedance in a cable mode.
摘要翻译：用于接收器电路的低噪声放大器（LNA）包括可调阻抗网络，其包括用于接收射频信号的输入，多个控制输入和输出。 LNA还包括耦合到多个控制输入并被配置为控制可调阻抗网络的阻抗的控制器。控制器控制可调阻抗网络以在地面模式中提供相对较低的阻抗并且在电缆模式中提供相对较高的阻抗。

36. 发明授权

US07904040B2 Receiver architectures utilizing coarse analog tuning and associated methods 有权
标题翻译：采用粗略模拟调谐和相关方法的接收机架构
公开(公告)号：US07904040B2
公开(公告)日：2011-03-08
申请号：US12004006
申请日：2007-12-19
申请人： Ramin Khoini-Poorfard , Andrew W. Krone
发明人： Ramin Khoini-Poorfard , Andrew W. Krone
IPC分类号： H04B7/08
CPC分类号： H04N5/4446 , H03D3/006 , H03D3/007 , H03L7/18 , H04H40/90 , H04N5/4401 , H04N5/50 , H04N7/20 , H04N21/4263
摘要： Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning of desired channels within a received signal spectrum, such as a set-top box signal spectrum for satellite communications. These architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) that provides a coarse tune analog mixing signal. Once mixed down, the desired channel may then be fine-tuned through digital processing, such as through the use of a wide-band analog-to-digital converter (ADC) or a narrow-band tunable bandpass ADC.
摘要翻译：公开了接收机架构和相关方法，其提供接收信号频谱内的期望信道的初始模拟粗调，例如用于卫星通信的机顶盒信号频谱。这些架构与先前的直接下变频（DDC）架构和低中频（IF）架构相比具有显着的优势，特别是在同一集成电路上需要两个调谐器的情况下。不是使用低IF频率或直接将期望的信道频率转换为DC，而是由模拟粗调谐电路提供的初始粗调调可以转换到大约DC的频率范围。该粗调谐电路可以例如使用提供粗调模拟混频信号的大步本地振荡器（LO）来实现。一旦混合，则可以通过数字处理（例如通过使用宽带模数转换器（ADC）或窄带可调谐带通ADC）来微调所需的信道。

37. 发明授权

US06909390B2 Digital-to-analog converter switching circuitry 有权
标题翻译：数模转换器开关电路
公开(公告)号：US06909390B2
公开(公告)日：2005-06-21
申请号：US10670160
申请日：2003-09-23
申请人： Ramin Khoini-Poorfard , Douglas R. Frey
发明人： Ramin Khoini-Poorfard , Douglas R. Frey
IPC分类号： H03M1/06 , H03M1/08 , H03M1/66
CPC分类号： H03M1/0678 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.
摘要翻译：用于用户线模拟前端的数模转换器电路包括差分放大器，开关电路和第一和第二电流转向数模转换器（DAC），每个DAC具有形成差分的第一和第二输出 DAC输出。开关电路将至少一个第一和第二DAC中的一个的差分输出耦合到一对开关节点。当所选DAC的差分输出耦合到该对开关节点时，另一DAC的差分输出短路。差分放大器的差分输入通信地耦合到该对交换节点。差分放大器的差分输出被耦合以驱动用户线的尖端线和环线。在各种实施例中，DAC，开关电路和差分放大器驻留在相同的半导体衬底上。

38. 发明申请

US20050020217A1 Communication terminal with low carrier feedthrough and communication system using such a terminal 审中-公开
标题翻译：具有低载波馈通的通信终端和使用这种终端的通信系统
公开(公告)号：US20050020217A1
公开(公告)日：2005-01-27
申请号：US10626063
申请日：2003-07-23
申请人： Ramin Khoini-Poorfard
发明人： Ramin Khoini-Poorfard
IPC分类号： H04B1/04 , H04L27/00 , H01Q11/12 , H04K1/02 , H04L25/03 , H04L25/49 , H04L27/04 , H04L27/36
CPC分类号： H04B1/0475 , H03F1/34 , H03F3/24 , H04B2001/0433 , H04L2027/0016 , H04L2027/0018
摘要： communication terminal (710) includes a coder (722, 724) receiving an input signal and having an output terminal for providing a coded signal; an upconverter core (100) having an input terminal for receiving a first signal having predetermined spectral content at an input frequency and an output terminal for providing an output signal having substantially the predetermined spectral content at a higher frequency using a local oscillator signal having a carrier frequency; an electrical measurement circuit having an input terminal coupled to the output terminal of the upconverter core (100), and an output terminal for providing a first offset correction signal representative of a power of the output signal at the carrier frequency; and a summing device (406) having a positive input terminal for receiving the coded signal, a negative input terminal coupled to the output terminal of the electrical measurement circuit, and an output terminal coupled to the input terminal of the upconverter core (100).
摘要翻译：通信终端（710）包括接收输入信号并具有用于提供编码信号的输出端的编码器（722,724）具有用于接收在输入频率处具有预定频谱含量的第一信号的输入端的上变频器内核（100）和用于使用具有载波的本地振荡器信号以较高频率提供具有基本上预定频谱含量的输出信号的输出端频率; 电测量电路，其具有耦合到所述上变频器内核（100）的输出端的输入端，以及输出端，用于提供表示所述载波频率处的所述输出信号的功率的第一偏移校正信号; 和具有用于接收编码信号的正输入端的求和装置（406），耦合到电测量电路的输出端的负输入端和耦合到上变频器芯（100）的输入端的输出端。

39. 发明授权

US06639534B2 Digital-to-analog converter switching circuitry 有权
标题翻译：数模转换器开关电路
公开(公告)号：US06639534B2
公开(公告)日：2003-10-28
申请号：US10076087
申请日：2002-02-14
申请人： Ramin Khoini-Poorfard , Douglas R. Frey
发明人： Ramin Khoini-Poorfard , Douglas R. Frey
IPC分类号： H03M166
CPC分类号： H03M1/0678 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.
摘要翻译：数模转换电路包括第一和第二DAC。在任何给定的时间，开关电路将选择的仅一个DAC的输出耦合到输出节点。在一个实施例中，第一DAC的第二输出在公共节点处耦合到第二DAC的第一输出。第一DAC的第一输出耦合到第一开关节点，并且第二DAC的第二输出耦合到第二开关节点。第一开关响应于第一开关信号将公共节点耦合到第一开关节点。响应于第二开关信号，第二开关将公共节点耦合到第二开关节点。开关信号确保在任何给定时间，公共节点通过第一和第二开关耦合到仅第一和第二开关节点中的一个。

40. 发明授权

US5986281A Circuit and method for predicting failure rates in a semiconductor device 失效
标题翻译：用于预测半导体器件中的故障率的电路和方法
公开(公告)号：US5986281A
公开(公告)日：1999-11-16
申请号：US956409
申请日：1997-10-23
申请人： William Edward Burchanowski , Jeffrey Alan Reed , Ramin Khoini-Poorfard
发明人： William Edward Burchanowski , Jeffrey Alan Reed , Ramin Khoini-Poorfard
IPC分类号： G01R31/28 , H01L21/00 , H01L21/66 , H01L23/58
CPC分类号： G01R31/2858
摘要： A circuit and method for detecting mobile ion contamination in a semiconductor device. The circuit uses two transistor structures on the same silicon chip as the circuit being tested to detect the presence (or absence) of mobile ions. The test includes imposing conditions on the silicon chip that may cause any mobile ions present therein to move within the structure. By measuring electrical parameters, such as a band gap voltage, across the transistors before and after the imposition of such conditions, a reliable indication of the presence or absence of mobile ions can be obtained.
摘要翻译：一种用于检测半导体器件中的移动离子污染的电路和方法。该电路在与被测电路相同的硅芯片上使用两个晶体管结构来检测移动离子的存在（或不存在）。测试包括在硅芯片上施加可能导致其中存在的任何移动离子在结构内移动的条件。通过在施加这种条件之前和之后测量跨越晶体管的电参数，例如带隙电压，可以获得是否存在移动离子的可靠指示。

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