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31. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

32. 发明授权

US06611050B1 Chip edge interconnect apparatus and method 失效
标题翻译：芯片边缘互连设备和方法
公开(公告)号：US06611050B1
公开(公告)日：2003-08-26
申请号：US09538636
申请日：2000-03-30
申请人： Thomas G. Ference , Wayne J. Howell , William R. Tonti , Richard Q. Williams
发明人： Thomas G. Ference , Wayne J. Howell , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2302
CPC分类号： H01L23/5388 , H01L21/561 , H01L21/78 , H01L23/3178 , H01L23/3185 , H01L24/03 , H01L24/11 , H01L25/0655 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0391 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/11312 , H01L2224/11332 , H01L2224/11334 , H01L2224/1134 , H01L2224/13 , H01L2224/13021 , H01L2224/13023 , H01L2224/13027 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/16054 , H01L2224/16105 , H01L2224/16137 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： The present invention provides a method of forming a low profile chip interconnection, and the interconnection so formed. A recessed contact area is formed at an edge of the wafer. A conductive material is deposited within the adjacent contact areas of each recess, thereby electrically connecting the two chips. The recess may have substantially perpendicular sides, or sloped sides.
摘要翻译：本发明提供一种形成低轮廓芯片互连的方法，以及形成的互连。在晶片的边缘处形成凹陷接触区域。导电材料沉积在每个凹槽的相邻接触区域内，从而电连接两个芯片。凹部可以具有大致垂直的侧面或倾斜的侧面。

33. 发明授权

US06445029B1 NVRAM array device with enhanced write and erase 失效
标题翻译： NVRAM阵列器件具有增强的写和擦除功能
公开(公告)号：US06445029B1
公开(公告)日：2002-09-03
申请号：US09695151
申请日：2000-10-24
申请人： Chung H. Lam , Richard Q. Williams
发明人： Chung H. Lam , Richard Q. Williams
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L27/115 , H01L29/42336
摘要： Increased write and erase tunnelling currents are developed by enhancement of an electric field near a floating gate with a shaped edge structure overlapping a source/drain diffusion and developing increased floating gate area with angled regions joined by edges in order to reduce write and erase cycle times. The edge structure is formed by selective and preferential etching in accordance with the crystal structure of a monocrystalline semiconductor substrate. The sharpness of the edges and concentration of the electric field may be enhanced by consumption and stress effects of oxidation of the substrate to form a floating gate insulator.
摘要翻译：增加的写和擦除隧道电流是通过增强浮置栅极附近的电场而形成的，具有与源极/漏极扩散重叠的成形边缘结构，并且通过边缘连接成角度的区域显影增大的浮动栅极区域，以减少写入和擦除周期时间。根据单晶半导体衬底的晶体结构，通过选择性和优先蚀刻形成边缘结构。边缘的锐度和电场的浓度可以通过基板的氧化的消耗和应力效应来增强，从而形成浮栅绝缘体。

34. 发明授权

US08453100B2 Circuit analysis using transverse buckets 失效
标题翻译：使用横向铲斗的电路分析
公开(公告)号：US08453100B2
公开(公告)日：2013-05-28
申请号：US12873554
申请日：2010-09-01
申请人： Dureseti Chidambarrao , Richard Q. Williams
发明人： Dureseti Chidambarrao , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region. The second region and the third region share perimeters in the second direction. The method then separately evaluates effects the other transistor elements have within each of the first region, the second region, and the third region, to determine a characteristic of the gate conductor.
摘要翻译：方法（和计算机程序）识别晶体管元件在几何电路布局内的形状和位置。晶体管元件包括有源区，至少一个栅极导体和其它晶体管元件。此外，栅极导体具有沿第一方向延伸的侧面，并且具有沿垂直于第一方向的第二方向延伸的宽度尺寸。该方法定义几何电路布局内的区域。为此，该方法限定了具有沿着栅极导体的侧面定位的周边的第一区域，其中栅极导体与有源区域相交，然后在第二方向上将第一区域的周边扩展到有源区域的边缘，以限定第二区域的周边。第一个区域和第二个共享周边的第一个方向。该方法然后在第一方向上扩展第二区域的周边以限定第三区域的周长。第二区域和第三区域在第二方向共享周边。该方法然后分别评估其它晶体管元件在第一区域，第二区域和第三区域内的效应，以确定栅极导体的特性。

35. 发明申请

US20120018806A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
标题翻译：具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法
公开(公告)号：US20120018806A1
公开(公告)日：2012-01-26
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

36. 发明授权

US07700410B2 Chip-in-slot interconnect for 3D chip stacks 失效
标题翻译：用于3D芯片堆栈的片上插槽互连
公开(公告)号：US07700410B2
公开(公告)日：2010-04-20
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L21/44
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

37. 发明申请

US20090144670A1 AUTOMATED OPTIMIZATION OF DEVICE STRUCTURE DURING CIRCUIT DESIGN STAGE 有权
标题翻译：电路设计阶段的器件结构自动优化
公开(公告)号：US20090144670A1
公开(公告)日：2009-06-04
申请号：US11946937
申请日：2007-11-29
申请人： Dureseti Chidambarrao , Jason Hibbeler , Richard Q. Williams
发明人： Dureseti Chidambarrao , Jason Hibbeler , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.
摘要翻译：提供了一种改进用于大规模集成电路的电路设计的方法，其表示在电路中互连的多个半导体器件。确定设计中的多个半导体器件中的一个的特征的边缘是否可以在第一方向上移动允许范围内的距离，使得提供电路的性能目标和匹配目标。如果是这样，边缘沿第一个方向移动计算的距离，以最佳地满足性能目标和匹配目标。对于多个半导体器件中的每一个可以重复上述步骤。如果需要，可以重复上述步骤，直到电路的性能目标和匹配目标被认为是充分的。

38. 发明授权

US07115968B2 Method of closing an antifuse using laser energy 失效
标题翻译：使用激光能量封闭反熔丝的方法
公开(公告)号：US07115968B2
公开(公告)日：2006-10-03
申请号：US10971238
申请日：2004-10-22
申请人： William T. Motsiff , William R. Tonti , Richard Q. Williams
发明人： William T. Motsiff , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译：一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。脉冲激光能量软化金属片段，静电场使金属片段彼此接触。静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

39. 发明授权

US06472230B2 Re-settable tristate programmable device 有权
标题翻译：可重新设置的三态可编程器件
公开(公告)号：US06472230B2
公开(公告)日：2002-10-29
申请号：US10102381
申请日：2002-03-20
申请人： Kurt R. Kimmel , J. Alex Chediak , William T. Motsiff , Wilbur D. Pricer , Richard Q. Williams
发明人： Kurt R. Kimmel , J. Alex Chediak , William T. Motsiff , Wilbur D. Pricer , Richard Q. Williams
IPC分类号： H01L2100
CPC分类号： H01L23/5258 , G11C11/5607 , G11C2216/26 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.
摘要翻译：一种用于可编程电路的方法和结构，其包括具有可改变的磁阻的磁性装置。

40. 发明授权

US06271059B1 Chip interconnection structure using stub terminals 有权
标题翻译：使用短截线端子的芯片互连结构
公开(公告)号：US06271059B1
公开(公告)日：2001-08-07
申请号：US09225148
申请日：1999-01-04
申请人： Claude L. Bertin , William R. Tonti , Richard Q. Williams
发明人： Claude L. Bertin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/05 , H01L24/81 , H01L2224/0401 , H01L2224/81136 , H01L2224/81141 , H01L2224/81192 , H01L2224/81365 , H01L2224/81801 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/19041
摘要： A method for fabricating a connector structure for interconnecting integrated circuit chips. The method includes the steps of patterning, masking and etching a substrate to form protrusions on the top and/or bottom surfaces of the substrate. Then the protrusions are preferentially etched to form truncated protrusions. An integrated circuit chip having pads on its surface is then joined to the top and/or bottom sides of the substrate. The protrusions and pads are coated with an electrically conductive metal. The substrate and the integrated circuit chips are joined and aligned together such that the truncated protrusions mate with the pads. Metal-coated vias are formed through the substrate to electrically connect the integrated circuit chips on the surfaces of the substrate.
摘要翻译：一种用于制造用于互连集成电路芯片的连接器结构的方法。该方法包括对衬底进行图案化，掩模和蚀刻以在衬底的顶表面和/或底表面上形成凸起的步骤。然后优先蚀刻突起以形成截短的突起。然后，在其表面上具有焊盘的集成电路芯片接合到衬底的顶部和/或底部。突起和垫被涂覆有导电金属。基板和集成电路芯片被接合并对齐在一起，使得截短的突起与焊盘配合。通过衬底形成金属涂覆的通孔，以电连接衬底表面上的集成电路芯片。

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