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31. 发明授权

US5742536A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5742536A
公开(公告)日：1998-04-21
申请号：US478416
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional damflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数阻力流中的后续移位量进一步复用，以在与最终分数位移量可用时基本相同的时间提供输出粘性位，从而与标准化分数基本上相同。

32. 发明授权

US5742535A Parallel calculation of exponent and sticky bit during normalization 失效
公开(公告)号：US5742535A
公开(公告)日：1998-04-21
申请号：US461676
申请日：1995-06-05
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.

33. 发明授权

US07952422B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US07952422B2
公开(公告)日：2011-05-31
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

34. 发明申请

US20090303778A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 审中-公开
公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

35. 发明授权

US06891399B2 Variable pulse width and pulse separation clock generator 失效
标题翻译：可变脉冲宽度和脉冲分离时钟发生器
公开(公告)号：US06891399B2
公开(公告)日：2005-05-10
申请号：US10388977
申请日：2003-03-13
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： G06F1/08 , H03K5/159 , H03K7/08 , H03K19/00 , G06F1/04 , H03H11/26 , H03K3/00
CPC分类号： G06F1/08 , H03K5/159 , H03K7/08
摘要： A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.
摘要翻译：提供了一种用于从全局时钟信号产生至少两个时钟脉冲信号的时钟脉冲发生器。时钟脉冲发生器包括用于接收具有上升沿和下降沿的时钟信号的至少一个输入端和用于可选地延迟与时钟信号的下降沿同步的脉冲信号的上升沿的机构。时钟脉冲发生器还包括与时钟信号的上升沿同步的第一可选择持续时间脉冲和与可选择地延迟的上升沿同步的第二可选择持续时间脉冲。时钟脉冲发生器还包括一个毛刺回避电路，用于消除时钟信号使用前的毛刺。

36. 发明授权

US06650145B2 Circuits and systems for limited switch dynamic logic 失效
标题翻译：有限开关动态逻辑的电路和系统
公开(公告)号：US06650145B2
公开(公告)日：2003-11-18
申请号：US10116612
申请日：2002-04-04
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： H03K1900
CPC分类号： H03K19/0963
摘要： Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.
摘要翻译：用于在动态逻辑器件的输出线上产生静态开关因子的电路和系统。实现具有动态部分和静态部分的逻辑设备。这样，只要设备执行的布尔运算的值不变，就保持输出逻辑状态。此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积，并且避免了对保持器装置的需要。

37. 发明授权

US06529084B1 Interleaved feedforward VCO and PLL 有权
标题翻译：交错前馈VCO和PLL
公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译：公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。传统的PLL设计被修改为将误差信号分成AC和DC分量。接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。

38. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

39. 发明授权

US06292027B1 Fast low-power logic gates and method for evaluating logic signals 失效
标题翻译：快速低功耗逻辑门和逻辑信号评估方法
公开(公告)号：US06292027B1
公开(公告)日：2001-09-18
申请号：US09440758
申请日：1999-11-16
申请人： Sand Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
发明人： Sand Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
IPC分类号： H03K19094
CPC分类号： H03K19/0013 , H03K19/0948
摘要： Fast low-power logic gates and method for evaluating logic signals reduce the effect of the power/speed tradeoff for parallel connected logic. A control circuit momentarily enables a high-current pullup or pulldown device after a connected input ladder switches from a conducting state to a non-conducting state. This allows a high current pullup or pulldown to be used for fast evaluation without increasing overall current drain, since the pullup action is momentary.
摘要翻译：快速低功耗逻辑门和逻辑信号评估方法降低并联连接逻辑电源/速度权衡的影响。在连接的输入梯形图从导通状态切换到非导通状态之后，控制电路暂时使能高电流上拉或下拉器件。这允许高电流上拉或下拉用于快速评估，而不会增加总体电流消耗，因为上拉动作是瞬时的。

40. 发明授权

US06282557B1 Low latency fused multiply-adder 失效
标题翻译：低延迟融合乘法加法器
公开(公告)号：US06282557B1
公开(公告)日：2001-08-28
申请号：US09207483
申请日：1998-12-08
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F748
CPC分类号： G06F7/5443 , G06F7/5318
摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
摘要翻译：公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

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