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31. 发明申请

WO2013163158A1 LOW SENSING CURRENT NON-VOLATILE FLIP FLOP APPARATUS COMPRISING MAGNETIC TUNNEL JUNCTIONS 审中-公开
标题翻译：包含磁性隧道结的低感测电流非挥发性飞溅装置
公开(公告)号：WO2013163158A1
公开(公告)日：2013-10-31
申请号：PCT/US2013/037764
申请日：2013-04-23
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Seong-Ook , JUNG, Youngdon , RYU, Kyungho , KIM, Jisu , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C7/06
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C14/0081
摘要： A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.
摘要翻译：低感测电流非易失性触发器包括用于感测两个磁性隧道结（MTJ）之间的电阻差的第一级和具有用于放大第一级的输出的电路的第二级。第一级的输出最初是预充电的，并且由感测操作开始时的两个MTJ的电阻差决定。第一级没有到源极电压（VDD）的上拉路径，因此在感测操作期间没有从VDD到地的直流路径。缓慢感应使能（SE）信号斜率可以降低第一级的峰值检测电流。次级电流路径减小了第一级的感测电流持续时间。

32. 发明申请

WO2012074537A1 MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 审中-公开
标题翻译：磁性隧道连接装置和制造
公开(公告)号：WO2012074537A1
公开(公告)日：2012-06-07
申请号：PCT/US2010/060590
申请日：2010-12-15
申请人： QUALCOMM INCORPORATED , LEE, Kangho , ZHU, Xiaochun , LI, Xia , KANG, Seung H.
发明人： LEE, Kangho , ZHU, Xiaochun , LI, Xia , KANG, Seung H.
IPC分类号： H01L43/10 , H01L43/12
CPC分类号： H01L43/10 , H01L43/12
摘要： A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer.
摘要翻译：公开了一种磁隧道结（MTJ）装置及其制造方法。在特定实施例中，公开了一种包括MTJ设备的设备。 MTJ装置包括阻挡层，自由层和镁（Mg）覆盖层。自由层位于阻挡层和镁（Mg）覆盖层之间。

33. 发明申请

WO2012048326A1 MAGNETIC RANDOM ACCESS MEMORY (MRAM) LAYOUT WITH UNIFORM PATTERN 审中-公开
标题翻译：具有均匀图案的磁性随机存取存储器（MRAM）布局
公开(公告)号：WO2012048326A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/055634
申请日：2011-10-10
申请人： QUALCOMM INCORPORATED , LEE, Kangho , KIM, Tae Hyun , LI, Xia , KIM, Jung Pill , KANG, Seung H.
发明人： LEE, Kangho , KIM, Tae Hyun , LI, Xia , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C5/02 , H01L27/02
CPC分类号： G11C5/025 , G11C5/08 , G11C11/165 , H01L27/0207 , Y10T29/49117
摘要： A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
摘要翻译：大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。大规模存储器阵列中的子阵列由虚拟位单元分隔开。信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

34. 发明申请

WO2011127025A1 ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS 审中-公开
标题翻译：磁性元件元件的不对称写入方案
公开(公告)号：WO2011127025A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031203
申请日：2011-04-05
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , RAO, Hari M. , KIM, Jung Pill , KANG, Seung H.
发明人： ZHU, Xiaochun , RAO, Hari M. , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
摘要翻译：对于磁性位单元元件定义非对称开关。用于存储器和其它器件的磁位单元包括耦合到MTJ结构的晶体管。位线在位单元的一个端子耦合到MTJ结构。在位单元的另一个端子处，源极线耦合到晶体管的源极/漏极端子。位线由提供第一电压的位线驱动器驱动。源极线由提供第二电压的源极线驱动器驱动。第二电压大于第一电压。通过将较高的第二电压施加到源极线和/或降低磁头单元元件中的整体寄生电阻的一个或组合来提高位单元和MTJ结构的开关特性并使其变得更可靠。

35. 发明申请

WO2011097455A1 MAGNETIC TUNNEL JUNCTION WITH DOMAIN WALL PINNING 审中-公开
标题翻译：磁性隧道结与领域墙壁钉扎
公开(公告)号：WO2011097455A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023713
申请日：2011-02-04
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , LI, Xia , KANG, Seung H.
发明人： ZHU, Xiaochun , LI, Xia , KANG, Seung H.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , H01L43/12
摘要： Magnetic tunnel junctions (MTJs) are manufactured having pinning sites in a ferromagnetic layer of the MTJ. The pinning sites are created using patterns in the photomask used during patterning of the ferromagnetic layer without adding additional processes to manufacturing of the MTJs. The pinning sites create energy barriers substantially preventing a domain wall in the ferromagnetic layer from passing into fixed regions of the ferromagnetic layer. Additionally, the pinning sites substantially prevent a domain wall in the ferromagnetic layer from returning to the middle of the free region. Pinning the domain wall at the boundary of the fixed region and the free region the ferromagnetic layer improves reliability and sensitivity of the MTJ. The ferromagnetic layer may be magnetized in a direction perpendicular to the plane of the ferromagnetic layer.
摘要翻译：在MTJ的铁磁层中制造具有钉扎位置的磁隧道结（MTJ）。使用在铁磁层的图案化期间使用的光掩模中的图案来创建钉扎位置，而不增加MTJ的制造的附加工艺。钉扎位置产生基本上阻止铁磁层中的畴壁进入铁磁层的固定区域的能量势垒。此外，钉扎位置基本上防止铁磁层中的畴壁返回自由区域的中间。固定区域边界处的固定区域和自由区铁磁层提高了MTJ的可靠性和灵敏度。铁磁层可以在垂直于铁磁层的平面的方向上被磁化。

36. 发明申请

WO2011091217A2 SYSTEM AND METHOD OF ADJUSTING A RESISTANCE-BASED MEMORY CIRCUIT PARAMETER 审中-公开
标题翻译：调整基于电阻的存储器电路参数的系统和方法
公开(公告)号：WO2011091217A2
公开(公告)日：2011-07-28
申请号：PCT/US2011/021988
申请日：2011-01-21
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H.
IPC分类号： G06F17/50 , G11C11/16 , G11C7/06
CPC分类号： G06F17/5036 , G06F2217/10 , G11C7/02 , G11C7/06 , G11C11/1673

37. 发明申请

WO2011088375A2 COMPOSITE HARDMASK ARCHITECTURE AND METHOD OF CREATING NON-UNIFORM CURRENT PATH FOR SPIN TORQUE DRIVEN MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：复合材料HARDMASK结构和创建非均匀电流路径的旋转扭矩驱动磁隧道结
公开(公告)号：WO2011088375A2
公开(公告)日：2011-07-21
申请号：PCT/US2011/021376
申请日：2011-01-14
申请人： QUALCOMM INCORPORATED , CHEN, Wei-Chuan , KANG, Seung H. , ZHU, Xiaochun
发明人： CHEN, Wei-Chuan , KANG, Seung H. , ZHU, Xiaochun
IPC分类号： H01L27/22 , G11C11/16 , H01F10/32 , H01L43/08 , B82Y25/00
CPC分类号： B82Y25/00 , B82Y10/00 , G11C11/161 , H01F10/3254 , H01F10/3272 , H01F41/32 , H01L43/08 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) storage element and method of forming the MTJ are disclosed. The magnetic tunnel junction (MTJ) storage element includesa pinned layer, a barrier layer, a free layer and a composite hardmask or top electrode. The composite hardmask / top electrode architecture is configured to provide a non-uniform current path through the MTJ storage element and is formed from electrodes having different resistance characteristics coupled in parallel. An optional tuning layer interposed between the free layer and the top electrode helps to reduce the damping constant of the free layer.
摘要翻译：公开了一种形成MTJ的磁隧道结（MTJ）存储元件和方法。磁性隧道结（MTJ）存储元件包括被钉扎层，阻挡层，自由层和复合硬掩模或顶部电极。复合硬掩模/顶电极结构被配置为提供穿过MTJ存储元件的不均匀电流路径，并且由具有并联耦合的不同电阻特性的电极形成。置于自由层和顶部电极之间的可选的调谐层有助于减小自由层的阻尼常数。

38. 发明申请

WO2011066324A2 MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 审中-公开
标题翻译：磁性隧道连接装置和制造
公开(公告)号：WO2011066324A2
公开(公告)日：2011-06-03
申请号：PCT/US2010/057891
申请日：2010-11-23
申请人： QUALCOMM Incorporated , LI, Xia , KANG, Seung H. , ZHU, Xiaochun
发明人： LI, Xia , KANG, Seung H. , ZHU, Xiaochun
IPC分类号： G11C11/15
CPC分类号： H01L43/12 , G11C11/15 , G11C11/161 , H01L21/00 , H01L27/224 , H01L43/08 , H04W52/12 , H04W52/26 , H04W52/34 , H04W52/44 , H04W52/54 , H04W72/1231 , H04W72/1247 , H04W72/1252 , H04W88/08 , H04W88/12
摘要： A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure above a bottom electrode. The method also includes forming a diffusion barrier layer above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer.
摘要翻译：公开了一种磁性隧道结（MTJ）器件及其制造方法。在特定实施例中，公开了一种方法，其包括在底部电极上形成磁性隧道结结构。该方法还包括在磁隧道结结构上方并邻近形成扩散阻挡层。该方法还包括蚀刻扩散阻挡层，去除在磁性隧道结结构上方的扩散阻挡层。该方法还包括将磁性隧道结结构的顶部连接到导电层。

39. 发明申请

WO2010053955A1 DATA PROTECTION DURING POWER-UP IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：旋转传动扭矩过程中的数据保护磁阻随机访问存储器
公开(公告)号：WO2010053955A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/063225
申请日：2009-11-04
申请人： QUALCOMM Incorporated , YOON, Sei Seung , KANG, Seung H.
发明人： YOON, Sei Seung , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C8/08 , G11C7/20 , G11C11/1653 , G11C11/1659 , G11C11/1675
摘要： A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells (420-432), a power-up controller (405), and a first plurality of precharge transistors (410-413) is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines (BL) and word lines (WL). The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.
摘要翻译：公开了包括多个位单元（420-432），上电控制器（405）和第一多个预充电晶体管（410-413）的自旋转移力矩磁阻随机存取存储器（STT-MRAM）阵列。多个比特单元各自耦合到多个位线（BL）和字线（WL）中的一个。上电控制器被配置为提供上电控制信号以在上电期间控制至少一个位线或字线的电压电平。第一多个预充电晶体管分别耦合到多个位线或多个字线中的至少一个，每个预充电晶体管被配置为基于功率放大晶体管将相应的位线或字线放电到期望的电压电平，控制信号。

40. 发明申请

WO2010036573A1 REDUCING SPIN PUMPING INDUCED DAMPING OF A FREE LAYER OF A MEMORY DEVICE 审中-公开
标题翻译：减少旋转泵浦引起的自由层的存储器件的阻尼
公开(公告)号：WO2010036573A1
公开(公告)日：2010-04-01
申请号：PCT/US2009/057467
申请日：2009-09-18
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , KANG, Seung H. , LI, Xia
发明人： ZHU, Xiaochun , KANG, Seung H. , LI, Xia
IPC分类号： G11C11/15 , G11C11/16 , H01L43/08
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01L43/08
摘要： A system and method of reducing spin pumping induced damping of a free layer (110) of a memory device (100) is disclosed. The memory device includes an anti-ferromagnetic material (AFM) pinning layer (104) in contact with a bit line access electrode (102). The memory device also includes a pinned layer (106) in contact with the AFM pinning layer, a tunnel barrier layer (108) in contact with the pinned layer, and a free layer (110) in contact with the tunnel barrier layer. The memory device includes a spin torque enhancing layer (112) in contact with the free layer and in contact with an access transistor electrode. The spin torque enhancing layer is configured to substantially reduce spin pumping induced damping of the free layer.
摘要翻译：公开了一种减小自旋泵送引起的阻塞存储器件（100）的自由层（110）的系统和方法。存储器件包括与位线接入电极（102）接触的反铁磁材料（AFM）钉扎层（104）。存储器件还包括与AFM钉扎层接触的钉扎层（106），与被钉扎层接触的隧道势垒层（108）以及与隧道势垒层接触的自由层（110）。存储器件包括与自由层接触并与存取晶体管电极接触的自旋转矩增强层（112）。自旋扭矩增强层被配置为基本上减少自由层的自旋泵送引起的阻尼。

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