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31. 发明申请

US20080005533A1 A METHOD TO REDUCE THE NUMBER OF LOAD INSTRUCTIONS SEARCHED BY STORES AND SNOOPS IN AN OUT-OF-ORDER PROCESSOR 失效
标题翻译：一种降低由订单处理者存储和销售商搜索的负载指令数量的方法
公开(公告)号：US20080005533A1
公开(公告)日：2008-01-03
申请号：US11427928
申请日：2006-06-30
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F15/00
CPC分类号： G06F9/3834
摘要： A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found.
摘要翻译：一种用于减少在由处理器执行加载指令时搜索的加载重新排序队列（LRQ）中的加载指令的数量的方法，包括分派加载指令; 以程序顺序插入LRQ中的加载指令; 清除负载接收的数据字段; 执行加载指令; 检查装载重新排序队列（LRQ）条目; 重新执行匹配LRQ条目的加载指令; 继续执行获取负载数据; 设置负载接收数据字段; 将每个加载指令的加载序列号（LSQN）与snoop_safe寄存器内容进行比较; 如果LSQN的幅度大于snoop_safe，则对所有加载接收数据位进行AND操作; 将snoop_safe寄存器设置为加载指令的LSQN; 搜索LRQ条目; 并将load_peril_snoop寄存器设置为找到snoop_safe较小的第一个加载指令的LRQ索引值。

32. 发明申请

US20060155932A1 Method and apparatus for an efficient multi-path trace cache design 失效
标题翻译：用于高效多路径跟踪缓存设计的方法和装置
公开(公告)号：US20060155932A1
公开(公告)日：2006-07-13
申请号：US11069014
申请日：2005-03-01
申请人： Galen Rasche , Jude Rivers , Vijayalakshmi Srinivasan
发明人： Galen Rasche , Jude Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

33. 发明申请

US20110320720A1 Cache Line Replacement In A Symmetric Multiprocessing Computer 审中-公开
标题翻译：对称多处理计算机中的缓存线替换
公开(公告)号：US20110320720A1
公开(公告)日：2011-12-29
申请号：US12821827
申请日：2010-06-23
申请人： Craig Walters , Vijayalakshmi Srinivasan
发明人： Craig Walters , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/123
摘要： Cache line replacement in a symmetric multiprocessing computer, the computer having a plurality of processors, a main memory that is shared among the processors, a plurality of cache levels including at least one high level of private caches and a low level shared cache, and a cache controller that controls the shared cache, including receiving in the cache controller a memory instruction that requires replacement of a cache line in the low level shared cache; and selecting for replacement by the cache controller a least recently used cache line in the low level shared cache that has no copy stored in any higher level cache.
摘要翻译：在对称多处理计算机中的高速缓存行替换，所述计算机具有多个处理器，在所述处理器之间共享的主存储器，包括至少一个高级私有高速缓存和低级共享高速缓存的多个高速缓存级别，以及控制共享缓存的高速缓存控制器，包括在高速缓存控制器中接收需要更换低级共享缓存中的高速缓存行的存储器指令; 并且通过高速缓存控制器选择在没有拷贝存储在任何更高级别的高速缓存中的低级共享高速缓存中的最近最少使用的高速缓存行。

34. 发明授权

US08004884B2 Iterative write pausing techniques to improve read latency of memory systems 有权
标题翻译：迭代写暂停技术来提高内存系统的读取延迟
公开(公告)号：US08004884B2
公开(公告)日：2011-08-23
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译：迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。恢复响应于保存的状态和要写入的数据。

35. 发明授权

US07962695B2 Method and system for integrating SRAM and DRAM architecture in set associative cache 失效
标题翻译： SRAM和DRAM架构在集合关联缓存中的集成方法和系统
公开(公告)号：US07962695B2
公开(公告)日：2011-06-14
申请号：US11949935
申请日：2007-12-04
申请人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
发明人： Marc R. Faucher , Hillery C. Hunter , William R. Reohr , Peter A. Sandon , Vijayalakshmi Srinivasan , Arnold S. Tran
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/123
摘要： A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.
摘要翻译：一种将混合体系结构集成在具有第一类型的存储器结构的集合关联高速缓存中的方法，所述第一类型的存储器结构用于每个同余类中的一种或多种方式，以及用于所述一致类的剩余方式的第二类型的存储器结构，包括确定存储器访问请求导致缓存命中或缓存未命中; 在高速缓存未命中的情况下，确定第一类型存储器结构的LRU方式是否也是整个同余类的LRU方式，如果不是，则将第一类型存储器结构的LRU方式的内容复制到LRU中并且在缓存未命中的情况下用新的高速缓存行填充第一类型存储器结构的LRU方式; 并根据存储器访问请求的结果更新LRU位。

36. 发明授权

US07930525B2 Method and apparatus for an efficient multi-path trace cache design 失效
标题翻译：用于高效多路径跟踪缓存设计的方法和装置
公开(公告)号：US07930525B2
公开(公告)日：2011-04-19
申请号：US12110745
申请日：2008-04-28
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

37. 发明授权

US07657726B2 Context look ahead storage structures 失效
标题翻译：前瞻性存储结构
公开(公告)号：US07657726B2
公开(公告)日：2010-02-02
申请号：US11923902
申请日：2007-10-25
申请人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Allan Mark Hartstein , Brian R. Prasky , Thomas Roberts Puzak , Moinuddin Khalil Ahmed Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F9/312
CPC分类号： G06F9/3806
摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.
摘要翻译：存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。第二个元结构与第一个元结构分层关联。第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

38. 发明申请

US20080313445A1 METHOD AND SYSTEM FOR PREVENTING LIVELOCK DUE TO COMPETING UPDATES OF PREDICTION INFORMATION 有权
标题翻译：用于预防活动的方法和系统，用于预测预测信息的更新
公开(公告)号：US20080313445A1
公开(公告)日：2008-12-18
申请号：US12051322
申请日：2008-03-19
申请人： ERIK R. ALTMAN , Vijayalakshmi Srinivasan
发明人： ERIK R. ALTMAN , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/528 , G06F9/30043 , G06F9/3842 , G06F9/3861
摘要： A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.
摘要翻译：防止活动锁的系统。预测事件的结果将形成事件结果预测。将事件结果预测与要访问的基准的正确值进行比较。当事件的结果被错误预测以形成附加的指令时，指令将附加真实的事件结果。在附加的指令上设置预测覆盖位。然后，附加的指令与实际事件结果一起执行。

39. 发明申请

US20080263326A1 METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN 失效
标题翻译：一种有效的多路追踪缓存设计方法与设备
公开(公告)号：US20080263326A1
公开(公告)日：2008-10-23
申请号：US12110745
申请日：2008-04-28
申请人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Galen A. Rasche , Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6022
摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.
摘要翻译：一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。此外，这些迹线的有效访问延迟减少了。

40. 发明申请

US20080010555A1 Method and Apparatus for Measuring the Cost of a Pipeline Event and for Displaying Images Which Permit the Visualization orf Said Cost 审中-公开
标题翻译：用于测量管道事件的成本和显示允许可视化或所述成本的图像的方法和装置
公开(公告)号：US20080010555A1
公开(公告)日：2008-01-10
申请号：US11424696
申请日：2006-06-16
申请人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F11/00
CPC分类号： G06F11/3423 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A hardware monitor is used to monitor the sequence of instructions executed during a miss cluster. The monitor groups each cache miss into a miss cluster, and the miss penalty associated with each cluster is determined by identifying a set of instructions that were executed during the miss cluster. The finite cache running time is then calculated for the set of instructions that occurred during the miss cluster. Additionally, an infinite cache running time is determined for the same set of instructions that occurred during the miss cluster, where the infinite cache running time is the time needed to execute this set of instructions in the absence of any miss. The cost of the miss cluster is then calculated by measuring the difference between the finite cache running time and the infinite cache running time.
摘要翻译：硬件监视器用于监视在小组群集期间执行的指令序列。监视器将每个高速缓存未命中组合成一个未命中集群，并且通过识别一组在缺少集群期间执行的指令来确定与每个集群相关联的丢失代价。然后针对在缺少集群期间发生的指令集计算有限缓存运行时间。另外，对于在缺少集群期间发生的相同指令集，确定无限缓存运行时间，其中无限高速缓存运行时间是在没有任何缺失的情况下执行该组指令所需的时间。然后，通过测量有限缓存运行时间和无限缓存运行时间之间的差异来计算小数簇的成本。

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