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31. 发明申请

US20110023003A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大型集成电路的精确寄生电容提取
公开(公告)号：US20110023003A1
公开(公告)日：2011-01-27
申请号：US12893870
申请日：2010-09-29
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

32. 发明授权

US07818698B2 Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确寄生电容提取
公开(公告)号：US07818698B2
公开(公告)日：2010-10-19
申请号：US11865304
申请日：2007-10-01
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

33. 发明申请

US20080161554A1 Macrocyclic carbodiimides (MC-CDI) and their derivatives, syntheses and applications of the same 失效
标题翻译：大环碳二亚胺（MC-CDI）及其衍生物，合成及应用相同
公开(公告)号：US20080161554A1
公开(公告)日：2008-07-03
申请号：US11646589
申请日：2006-12-28
申请人： Shenghong A. Dai , Chih-Chia Cheng , Chien-Wen Chen , Chih-Hung Chen
发明人： Shenghong A. Dai , Chih-Chia Cheng , Chien-Wen Chen , Chih-Hung Chen
IPC分类号： C07D273/00 , C07D267/22
CPC分类号： C08G18/4825 , C08G18/10 , C08G18/7621 , C08G18/797 , C08G18/025
摘要： Disclosed are a macrocyclic carbodiimide (MC-CDI) and a process for synthesizing the same through condensation of a molecule with multiple-isocyanate terminal functional groups under high dilution in the presence of a phospholene catalyst such as phospholene or arsenic catalyst. Also disclosed are MC-CDI derivatives, such as MC-urea (MC-U), MC-acylurea (MC-ACU), acid functionalized MC-ACU, and anhydride functionalized MC-ACU, processes for synthesizing the same, and the applications of such derivatives as hydrolysis stabilizers in organic polymeric materials, such as polyurethane (PU) and polyesters, as well as the applications in the syntheses of the amide- and imide-modified polyurethane by ring-opening reaction of the MC-ACU.
摘要翻译：公开了一种大环碳二亚胺（MC-CDI）及其通过在磷酸催化剂如磷酰或砷催化剂存在下在高稀释度下通过分子与多异氰酸酯末端官能团的缩合来合成它的方法。还公开了MC-CDI衍生物，例如MC-脲（MC-U），MC-酰基脲（MC-ACU），酸官能化的MC-ACU和酸酐官能化的MC-ACU，其合成方法和应用的有机聚合材料如聚氨酯（PU）和聚酯中的水解稳定剂的衍生物，以及通过MC-ACU的开环反应合成酰胺和酰亚胺改性的聚氨酯的应用。

34. 发明申请

US20060188824A1 Method for improving design window 有权
标题翻译：改善设计窗口的方法
公开(公告)号：US20060188824A1
公开(公告)日：2006-08-24
申请号：US11320513
申请日：2005-12-27
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： G03F7/00
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

35. 发明授权

US06855967B2 Utilization of MACRO power routing area for buffer insertion 有权
标题翻译：利用MACRO电源路由区进行缓冲区插入
公开(公告)号：US06855967B2
公开(公告)日：2005-02-15
申请号：US10283892
申请日：2002-10-30
申请人： Louis Chao-Chiuan Liu , Chien-Wen Chen
发明人： Louis Chao-Chiuan Liu , Chien-Wen Chen
IPC分类号： H01L23/528 , H01L27/10 , H01L23/04 , H01L23/48 , H01L23/52
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.
摘要翻译：用于在宏块区域中的宏小区之间的电力线区域中形成缓冲单元的结构和方法。在电源线电平上，在VSS和VDD线之间形成一个引脚。引脚连接到缓冲单元。接下来，形成信号线层，信号线连接到引脚和驱动器。在第一实施例中，驱动器形成在标准单元区域中。在第二实施例中，驱动器形成在宏小区中。信号线连接到引脚和驱动器。

36. 发明授权

US08518722B2 Method for detecting the under-fill void in flip chip BGA 有权
标题翻译：用于检测倒装芯片BGA中欠补充空隙的方法
公开(公告)号：US08518722B2
公开(公告)日：2013-08-27
申请号：US13064161
申请日：2011-03-09
申请人： Chien-Wen Chen , Chia-Jen Kao , Jui-Cheng Chuang
发明人： Chien-Wen Chen , Chia-Jen Kao , Jui-Cheng Chuang
IPC分类号： H01L21/66
CPC分类号： H01L23/49816 , H01L21/563 , H01L22/12 , H01L23/055 , H01L23/49827 , H01L24/81 , H01L2224/16235 , H01L2224/16238 , H01L2224/8123 , H01L2224/81815 , H01L2224/81908 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01074 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.
摘要翻译：提供了一种用于检测倒装芯片球栅阵列封装结构的欠补充空隙的方法，其包括在其中提供具有互连结构的衬底和多个中介层; 提供具有活性表面和背面的芯片，以及在芯片的有源表面上的多个第一连接元件; 将所述芯片的有源表面安装并电连接在所述基板上; 执行至少一次IR回流以将所述多个第一连接元件固定在所述基板上; 填充封装材料以覆盖所述芯片的有效表面和所述多个第一连接元件; 执行检测处理以检测在所述芯片的有效表面和所述多个第一元件之间不形成所述空隙; 以及在所述基板的背面上形成多个第二连接元件以获得倒装芯片球栅阵列封装结构。

37. 发明授权

US08214784B2 Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确寄生电容提取
公开(公告)号：US08214784B2
公开(公告)日：2012-07-03
申请号：US12893870
申请日：2010-09-29
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

38. 发明申请

US20110176777A1 Apparatus For Optical Fiber Connection 审中-公开
标题翻译：光纤连接装置
公开(公告)号：US20110176777A1
公开(公告)日：2011-07-21
申请号：US12704549
申请日：2010-02-12
申请人： Chien-Wen Chen
发明人： Chien-Wen Chen
IPC分类号： G02B6/38
CPC分类号： G02B6/3825 , G02B6/3874
摘要： An apparatus for optical fiber connection is provided, including a shell base and at least an optical fiber coupling tube. The inner shape and the outer shape of the shell base are made according to the different types of optical fiber connection apparatus specifications. The optical fiber coupling tube is fixed to the inside of the shell base. The optical fiber tube includes a hard tube wall along the axis of the tube and at least a deformable tube wall. The deformable tube wall is resilient and can be slightly deformed and restored to original shape. When used for connecting optical fibers, the present invention provides precise positioning and the optical signal loss and pulling torque are all within specifications.
摘要翻译：提供了一种用于光纤连接的设备，包括壳体基底和至少一个光纤耦合管。根据不同类型的光纤连接设备规格，制造壳体的内部形状和外形。光纤耦合管固定在壳体的内部。光纤管包括沿着管的轴线的硬管壁和至少一个可变形的管壁。可变形管壁是弹性的，可以稍微变形并恢复到原来的形状。当用于连接光纤时，本发明提供精确的定位，并且光信号的损失和拉动扭矩都在规格范围内。

39. 发明申请

US20100302749A1 Controlling Warpage in BGA Components in a Re-flow Process 有权
标题翻译：控制回流过程中BGA组件的翘曲
公开(公告)号：US20100302749A1
公开(公告)日：2010-12-02
申请号：US12730857
申请日：2010-03-24
申请人： Chia-Jen Kao , Chen-Fa Tsai , Chien-Wen Chen
发明人： Chia-Jen Kao , Chen-Fa Tsai , Chien-Wen Chen
IPC分类号： H05K7/00 , H01R43/00
CPC分类号： H01L21/563 , H01L23/49816 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01087 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/18161 , H01L2924/3511 , H05K3/305 , H05K3/3436 , H05K3/3494 , H05K2201/10734 , Y02P70/613 , Y10T29/49117 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.
摘要翻译：制造集成电路封装的方法包括：在BGA模块的一侧提供包括BGA球的球栅阵列（BGA）模块; 提供基底; 并将BGA模块放置在基底基板上。 BGA球放置在BGA模块和基底之间。粘合剂施加在BGA模块和基底基板之间并与之接触。然后将粘合剂固化。在固化粘合剂的步骤之后，BGA球再次流动。

40. 发明授权

US07598360B2 Bisstyryl compound and high density recording media utilizing the same 失效
标题翻译：双苯乙烯基化合物和利用其的高密度记录介质
公开(公告)号：US07598360B2
公开(公告)日：2009-10-06
申请号：US11254663
申请日：2005-10-21
申请人： Shin-Shin Wang , Chien-Wen Chen , Jong-Lieh Yang , Chii-Chang Lai , Hui-Ping Tsai , Wen-Ping Chu , Wen-Yih Liao , Chien-Liang Huang , Tzuan-Ren Jeng , Ching-Yu Hsieh , An-Tse Lee
发明人： Shin-Shin Wang , Chien-Wen Chen , Jong-Lieh Yang , Chii-Chang Lai , Hui-Ping Tsai , Wen-Ping Chu , Wen-Yih Liao , Chien-Liang Huang , Tzuan-Ren Jeng , Ching-Yu Hsieh , An-Tse Lee
IPC分类号： C07D403/06 , C07D401/14 , B32B3/02
CPC分类号： G11B7/246 , C09B23/0091 , C09B69/045 , C09B69/06 , G11B7/2467 , G11B7/2472 , G11B7/2478 , G11B7/2495 , G11B7/2533 , G11B7/2534 , G11B7/2535 , G11B7/2585 , G11B7/259 , G11B7/2595 , G11B2007/24612 , Y10S430/146
摘要： A bisstyryl compound. The bisstyryl compound has formula (I): wherein Z1 and Z2 are benzene, naphthalene, or heterocyclic ring, R1 is H, C1-5 alkyl, hydroxyl, halogen atoms, or alkoxy, R2 is H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, sulfuric ester, amide, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R3, R4, R5, and R6 are H, halogen atoms, alkyl, aralkyl, or heterocyclic ring containing O, S, or N, or R3 and R4 are joined to a nitrogen atom or R5 and R6 are joined together to form a ring, R7 and R8 are H or alkyl, W is nitrogen with or without Z1 and Z2 or aromatic group without Z1 and Z2, Y is carbon, oxygen, sulfur, selenium, —NR, or —C(CH3)2, m is 1-3, n is 1-18, and X1 and X2 are anionic groups or anionic organometallic complexes.
摘要翻译：双苯乙烯基化合物。双苯乙烯基化合物具有式（I）：其中Z 1和Z 2是苯，萘或杂环，R 1是H，C 1-5烷基，羟基，卤素原子或烷氧基，R 2是H，卤素原子，C 1-5烷基硝基，酯，羧基，磺基，磺酰胺，硫酸酯，酰胺，C 1-3烷氧基，氨基，烷基氨基，氰基，C 1-6烷基磺酰基或C 2-7烷氧基羰基，R 3，R 4，R 5和R 6是H，含有O，S或N或R 3和R 4的卤素原子，烷基，芳烷基或杂环与氮原子连接或R 5和R 6连接在一起形成环，R 7和R 8为H或烷基，W为具有或不具有Z 1和Z 2或不具有Z 1和Z 2的芳族基团的氮，Y为碳，氧，硫，硒，-NR或-C（CH 3）2，m为1-3，n为1-18，X1为 X2是阴离子基团或阴离子有机金属络合物。

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